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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com ? ? ? ? XRT4500 multiprotocol serial network interface ic september 2002 rev. 1.0.7 general description the XRT4500 is a fully integrated multiprotocol serial interface. it supports all of the popular serial commu- nication interface standards such as itu-t v.35, itu- t v.36, eia530a, rs232 (itu-t v.28), itu-t x.21 and rs449. it can easily be interfaced with most common types of serial communications controllers (sccs). this device contains eight receivers and eight transmitters, in groups of six or seven. it is a complete solution containing all of the required source and load termination resistors in one 80-pin tqfp package. the XRT4500 operates at higher speeds (20mhz for v.35 and 256kbps for v.28). the XRT4500 can be configured to operate in one of the seven interface standards in either dte, or dce modes of operation and power down mode. it fully supports echoed clock as well as clock and data in- version. loopbacks are supported in dte and dce modes of operation. this feature eliminates the need for external circuitry for loopback implementation. control signals such as ri, rl, dcd, dtr, dsr are protected against glitches by internal filters. these fil- ters can be turned off. the XRT4500 provides an in- ternal oscillator (clock signal) which can be used to conduct standalone diagnostics of dte equipment. b lock d iagram features ? pin programmable multiprotocol serial interface ? v.35, v.36, eia-530 a, rs232 (v.28), v.10, v.11, x.21 and rs449 communication interface standards ? v.28, v.10, v.11 and v.35 electrical interfaces are ctr2 compliant ? contains on-chip source and load termination resistors ? contains eight receivers and eight transmitters with switchable dte and dce modes ? glitch filters on the control signals (selectable) ? +5v single power supply with internal dc-dc converter ? full support of loopbacks, data & clock inversion, and echoed clock in dte and dce modes ? full support of most popular types of hdlc control- lers (single, double, and triple clocks supported) ? high-speed v.28 driver: 256khz ? internal oscillator for standalone dte loopback te s t i n g ? control signals can be registered and non-regis- tered ? control signals can be tri-stated for bus-based designs ? cable safe operation supported ? esd protection over 1kv range ? ttl level digital inputs ? ttl/cmos digital outputs applications ? data service units (dsu) ? channel service units (csu) ? routers ? bridges ? access equipment tx2 tx1 rx3 rx2 rx1 tx4 tx3 rx4 rx5 tx5 tx6 rx6 tx7 rx8 rx7 v.10, v.11, v.35, v.28 electrical interfaces si g nals txd, rxd high speed data a n d c l oc k v.10, v.11, v.35, v.28 v.10, v.11, v.35, v.28 scte signals: dce transmitter, dte receiver rts, cts dtr, dsr ll, rl, ri (tm) ll, rl, ri (tm) mode and configuration control switching regulator dc-dc converter v.10, v.11, ---- , v.28 v.10, v.11, ---- , v.28 v.10, v.11, ---- , v.28 v.10, ---- , ---- , v.28 v.10, ---- , ---- , v.28 high speed transceiver txc, rxc high speed data and clock dcd signals: dce transmitter, dte receiver diagnostic transceivers tx8 handshaking/control transceivers
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 2 b lock d iagram digital mux 1 47m f low esr -6v 26 -6v switching regulator 41 56 52 42 43 +12v charge pump 21 22 2.2 m f v ss vsense v ss _t123 sr_out isense gnd_reg cpp cpm 1n5819 47 m h 0.5 w - + 16 decoder latch 4 5 6 44 XRT4500 mode & configuration control logic 32 - 64 khz slew rate control 45 39 r slew m0 m1 m2 clkfs slew_cntl mode select echo clock 34 2 or 3 clock select 50 invert clock 54 register 24 invert data 55 loopback register mode clock input mode control 49 reg_clk reg 2ck/3ck lp clk inv dt inv ec dec/dte 51 vdd_reg vdd rx1b rx1,2,3 rx1d rx1a 2 78 79 rx2d rx1 1 rx8d rx8i 25 23 rx8 filter gnd rx1,2,3 3 rx5b rx5d rx5a 36 33 35 rx5 filter rx2b rx2a t 77 74 76 rx2 rx3d 73 rx3 rx67d 32 rx4,5,6,7 rx7 rx6 filter filter 75 en_fltr tx1,2,3 58 vdd_t123 67 tx2d t 64 tx2a 66 cm_tx2 tx2b 65 68 tx3d t 70 tr3a 69 cm_tr3 tr3b 71 8 tx4d 11 tx4a tx4b 10 tx2 tx4 tx3 15 tx5d 12 tx5a tx5b 13 27 tr7 tx7 tx5 gnd_t12 60 tx1d t 63 tx1a 61 cm_tx1 tx1b 62 tx1 tx1,2 59 72 gnd 9 vdd tx4,5,6,7,8 29 tr6a tr6b 30 tx6 mux 28 tx76d v.11 (rx1,2,3) termination 80 en_term digital mux 2 46 glitch filter 48 en_out mux e_232h oscen 53 tx1,2,3 57 gnd rx4,5,6,7,8 7 v ss 17 tx8d 19 tx8o gnd 14 tx4,5,6,7,8 tx8 t high speed rs232 enable 20 vdd rx4b rx4d rx4a 37 40 38 rx4 filter v pp + 10 m f 0.1 0.1 0.1 vdd 47 latch mode control mux control 18 31 500 khz clock + -
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 3 p in o ut of the d evice o rdering i nformation p art n umber p ackage o perating t emperature r ange XRT4500cv 80 pin tqfp 0 c to +70 c cpp cpm rx8d reg rx8i vss tr7 tx76d tr6a tr6b dce/dte rx67d rx5d ec rx5b rx5a rx4a rx4b slew_cntl rx4d XRT4500 80 lead tqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 en_term rx1b rx1a rx2a rx2b en_fltr rx2d rx3d gnd tr3b tr3a cm_tr3 tx3d tx2d cm_tx2 tx2b tx2a tx1a tx1b cm_tx1 vdd tx8o lp tx8d vpp tx5d gnd tx5b tx5a tx4a tx4b vdd tx4d bias m2 m1 m0 gnd vdd rx1d tx1d gnd vdd gnd vss dtinv ckinv oscen sr_out vdd 2ck/3ck reg_clk en_out vdd e-232 clkfs latch gnd i_sense v_sense
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XRT4500 multiprotocol serial network interface ic rev. 1.0.7 i table of contents general description................................................................................................. 1 block diagram.................................................................................................................. ......................... 1 f eatures ............................................................................................................................... ....... 1 a pplications ............................................................................................................................... .1 block diagram.................................................................................................................. ......................... 2 pin out of the device .......................................................................................................... ...................... 3 ordering information ........................................................................................................... ...................... 3 t able of c ontents ............................................................................................................ i pin descriptions .......................................................................................................... 4 e lectrical c haracteristics .................................................................................................... 26 ta = 25c, vdd = 5v, vss = -6v, vpp = 12v, maximum operating frequency unless otherwise specified 28 power supply consumption....................................................................................................... ............. 29 f igure 1. s upply c urrent versus t emperature and s upply v oltage , without l oad or s ignal in eia-530 (v.11) mode ............................................................................................................................... .......................... 29 f igure 2. s upply c urrent versus t emperature and s upply v oltage , with l oad in eia-530 (v.11) mode ... 30 f igure 3. rs422 d river t est c ircuit ................................................................................................................. 33 f igure 4. rs422 d river /r eceiver ac t est c ircuit ........................................................................................... 33 f igure 5. v.35 d river /r eceiver ac t est c ircuit (tx1/rx1, tx2/rx2 o nly ) .................................................. 34 f igure 6. v.10/v.28 d river t est c ircuit ............................................................................................................ 34 f igure 7. v.10 (rs-423) v.28 (rs-232) r eceiver t est c ircuit ......................................................................... 34 f igure 8. v.11, v.35 d river p ropagation d elays .............................................................................................. 34 f igure 9. v.11, v.35 r eceiver p ropagation d elays .......................................................................................... 34 f igure 10. v.10 (rs-423) v.28 (rs-232) d river p ropagation d elays ............................................................. 35 f igure 11. v.10, v.28 r eceiver p ropagation d elays ........................................................................................ 35 t able 1: r eceiver s pecifications ....................................................................................................................... 35 t able 2: t ransmitter s pecification .................................................................................................................... 36 1.0 system description ...................................................................................................... ............... 37 1.1 the difference between an electrical interface and a communications interface 37 t able 3: dte m ode - c ontrol p rogramming for d river and r eceiver m ode s election .............................. 38 t able 4: dce m ode - c ontrol p rogramming for d river and r eceiver m ode s election .............................. 38 1.2 the system architecture ................................................................................................. ................... 39 1.2.1 the high -speed transceiver block .................................................................................... ..................... 40 f igure 12. h igh -s peed t ransceiver b lock ........................................................................................................ 40 1.2.2 the handshaking/control signal transceiver block .................................................................... 41 f igure 13. h andshaking /c ontrol t ransceiver b lock ...................................................................................... 41 1.2.3 the diagnostic operation indicator transceiver block............................................................... 4 2 f igure 14. d iagnostic o peration indicator t ransceiver b lock ..................................................................... 42 1.3 the control block ....................................................................................................... .......................... 43 f igure 15. d iagram of the XRT4500 c ontrol b lock ........................................................................................ 43 1.3.1 m[2:0] - the (communication interface) mode control select pins. ............................................... 44 t able 5: t he r elationship between the settings for the m[2:0] bit - fields and the c orresponding c ommunica - tion i nterface that is supported .......................................................................................................... 44 1.3.2 dce/dte - the dce/dte mode select pin .................................................................................. ...................... 45 f igure 16. a s imple i llustration of the dce/dte i nterface .......................................................................... 45 1.3.3 the lp - loop-back enable/disable select pin ........................................................................... ............. 46 f igure 17. i llustration of both the dte and dce m ode XRT4500 operating , when the l oop -b ack m ode is dis - abled ............................................................................................................................... ......................... 46 f igure 18. i llustration of the b ehavior the dte m ode XRT4500, when it is configured to operate in the l oop - b ack m ode ............................................................................................................................... ................ 47 f igure 19. i llustration of the b ehavior of the dce m ode XRT4500, when it is configured to operate in the l oop - back m ode ............................................................................................................................... ....... 48 1.3.4 the ec* (echo clock mode - enable/disable select input pin) .......................................................... 4 9 f igure 20. i llustration of a typical 3-c lock dce/dte i nterface ............................................................... 49 f igure 21. i llustration of the wave - forms of the signals that are transported across a 3-c lock dte/dce i nterface ............................................................................................................................... .................. 50
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 ii f igure 22. i llustration of a 2-c lock dte/dce i nterface ............................................................................ 51 f igure 23. t he b ehavior of the txc and txd s ignals at the dce and dte scc s , (d ata r ate = 1.0m bps , dce- to -dte propagation delay = 160 ns , dte- to -dce propagation delay = 160 ns )............................ 52 f igure 24. t he b ehavior of the txc and txd s ignals at the dce and dte scc s (d ata r ate = 1.544m bps , dce- to -dte p ropagation d elay = 160 ns , dte- to -dce p ropagation d elay = 160 ns ) ............................. 52 f igure 25. i llustration of the e cho -c lock f eature within the XRT4500 ................................................... 53 f igure 26. i llustration of the w ave - forms , across a dce/dte i nterface , when the e cho -c lock f eature ( within the XRT4500) is used as depicted in f igure 25........................................................................ 54 1.3.5 the 2ck/3ck (2-clock/3-clock mode - enable/disable select input pin) ..................................... 54 f igure 27. i llustration of the dce/dte i nterface , with the dce m ode XRT4500 operating in the 2-c lock m ode ............................................................................................................................... ......................... 55 1.3.6 the clock inversion (ck_inv) feature ................................................................................. .................... 55 f igure 28. i llustration of the dce m ode XRT4500 being configured to invert the txc signal ................ 56 f igure 29. i llustration of the dte m ode XRT4500 being configured to invert the txc signal ................ 56 f igure 30. i llustration of the dce m ode XRT4500, which is operating in the 2-c lock m ode , and inverting the txc signal ............................................................................................................................... ...... 57 1.3.7 the latch mode of operation ............................................................................................ ............................ 58 1.3.8 the registered mode of operation ....................................................................................... ...................... 58 f igure 31. a n i llustration of the e ffective i nterface between the XRT4500 and the scc/m icroprocessor when the r egistered m ode is enabled ............................................................................................... 58 f igure 32. a n i llustration of the n ecessary g lue l ogic required to design a feature similar to that offered by the r egistered m ode , when using a different m ulti - protocol s erial n etwork i nterface ic 59 1.3.9 the internal oscillator ................................................................................................ .................................. 59 f igure 33. i llustration of the i nternal o scillators within the XRT4500..................................................... 60 1.3.10 glitch filters........................................................................................................ .............................................. 60 1.3.11 data inversion ........................................................................................................ ............................................ 60 1.3.12 data interlude ........................................................................................................ ........................................... 60 2.0 receiver and transmitter specifications .........................................................................60 3.0 v.10\v.28 output pulse rise and fall time control .........................................................60 f igure 34. v.10 r ise /f all t ime as a f unction of rslew ................................................................................. 61 f igure 35. v.28 s lew r ate o ver 3 v o utput r ange with 3 k w in p arallel with 2500 p f l oad as a f unction of rslew......................................................................................................................... ....................... 61 4.0 the high-speed rs232 mode ............................................................................................... .........61 5.0 internal cable terminations ............................................................................................. .....62 6.0 operational scenarios ................................................................................................... ...........62 7.0 applications information ................................................................................................ .........62 f igure 36. r eceiver t ermination ........................................................................................................................ 63 t able 6: r eceiver s witches ............................................................................................................................... .63 f igure 37. t ransmitter t ermination .................................................................................................................. 64 t able 7: t ransmitter s witches ........................................................................................................................... 64 f igure 38. t ypical v.10 or v.28 i nterface (r1 = 10 kw in v.10 and 5 kw in v.28) ........................................ 64 f igure 39. t ypical v.11 i nterface (t ermination r esistor , r1, is o ptional .).................................................. 64 f igure 40. t ypical v.35 i nterface ...................................................................................................................... 65 t able 8: mux1 c onnection t able ....................................................................................................................... 65 t able 9: mux2 c onnection t able (rx4-rx7, tx4-tx7), o utput v ersus i nput .............................................. 67 f igure 41. s cenario a, mux2, (dce/dte = 0, lp = 0)....................................................................................... 68 f igure 42. s cenario b, mux2, (dce/dte = 0, lp = 1), l oop b ack n ot enabled ............................................. 69 f igure 43. s cenario c, mux2, (dce/dte = 1, lp = 0)....................................................................................... 70 f igure 44. s cenario d, mux2, (dce/dte = 1, lp = 1), l oop b ack n ot enabled ............................................. 71 f igure 45. s erial i nterface s ignals and c onnector p in -o ut ......................................................................... 72 f igure 46. s erial i nterface c onnector d rawings ........................................................................................... 73 f igure 47. eia-530 c onnection d iagram for XRT4500 .................................................................................... 74 f igure 48. rs-232 c onnection d iagram for XRT4500 ..................................................................................... 75 scenarios 1 & 2 normal: 3-clock dce/dte interface operation ...........................................................76 input pin settings ............................................................................................................. .......................76 scenario 3 &2 dte loop-back mode............................................................................................... .......77 input pin settings ............................................................................................................. .......................77 scenario 4 ..................................................................................................................... ..........................78 comments: dce loop-back mode ................................................................................................... ......78
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XRT4500 multiprotocol serial network interface ic rev. 1.0.7 iii input pin settings ............................................................................................................. ....................... 78 scenario 5 & 2................................................................................................................. ........................ 79 comments: txc clock inversion in dte mode ...................................................................................... 79 input pin settings ............................................................................................................. ....................... 79 scenario 6 ..................................................................................................................... .......................... 80 comments: txc clock inversion in dce mode...................................................................................... 80 input pin settings ............................................................................................................. ....................... 80 scenario 7 & 2................................................................................................................. ........................ 81 input pin settings ............................................................................................................. ....................... 81 scenario 8 ..................................................................................................................... .......................... 82 input pin settings ............................................................................................................. ....................... 82 scenario 9 & 10................................................................................................................ ....................... 83 comments: 2 clock mode operation within the dce mode. this feature is useful for applications .. 83 that interface to a device which does not supply scte clock signal............................................... 83 input pin settings ............................................................................................................. ....................... 83 scenario 12 .................................................................................................................... ......................... 84 input pin settings ............................................................................................................. ....................... 84 scenario 13 & 10............................................................................................................... ...................... 85 input pin settings ............................................................................................................. ....................... 85 scenario 14 .................................................................................................................... ......................... 86 comments: txc clock inversion and 2 clock mode operation within the dce mode. this scenario can be used to resolve the 2 clock propagation delay timing violation issue. .......................................... 86 input pin settings ............................................................................................................. ....................... 86 scenario 16 .................................................................................................................... ......................... 87 input pin settings ............................................................................................................. ....................... 87 scenario 17 & 18............................................................................................................... ...................... 88 comments: x:21 mode operation.................................................................................................. ......... 88 input pin settings (1 clock mode) .............................................................................................. ............. 88 scenario 20 .................................................................................................................... ......................... 89 input pin settings (1 clock mode) .............................................................................................. ............. 89 scenario 21 .................................................................................................................... ......................... 90 input pin settings (1 clock mode) .............................................................................................. ............. 90 scenario 22 .................................................................................................................... ......................... 91 input pin settings (1 clock mode) .............................................................................................. ............. 91 scenario 23 .................................................................................................................... ......................... 92 input pin settings (1 clock mode) .............................................................................................. ............. 92 scenario 48 .................................................................................................................... ......................... 93 input pin settings (1 clock mode) .............................................................................................. ............. 93 r evisions ............................................................................................................................... .... 96
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 4 pin descriptions pin # signal dte mode dce mode type function 1 rx1d d_rxd d_txd o receiver 1 digital output C digital data output to terminal equipment this output pin is the digital (ttl/cmos level) representation of the line signal that has been received via the rx1a (pin 78) and rx1b (pin 79) input pins. the exact role that this pin plays depends upon whether the XRT4500 is operating in the dce or dte mode. dce mode C txd digital output signal this output pin functions as the txd digital output signal (which should be input to the terminal equipment). dte mode C rxd digital output signal this output pin functions as the rxd digital output signal (which should be input to the terminal equipment). 2vdd analog vdd for receiver 1, 2, 3 3gnd i analog gnd for receiver 1, 2, 3 and transmitter 3 4m0 i mode control C mode select input 0 this input pin, along with m1 and m2 are used to configure the XRT4500 to operate in the desired communication interface mode. table 3 and table 4 present the relationship between the states of the m2, m1 and m0 input pins and the correspond- ing communication interface modes selected. this input pin (along with m1 and m2) is internally latched into the XRT4500, upon the rising edge of the latch signal. at this point, changes in this input pin will not effect the internally latched state of this pin. this input pin contains an internal 20k w pull-up to vdd. 5m1 i mode control C mode select input 1 this input pin, along with m0 and m2 are used to configure the XRT4500 to operate in the desired communication interface mode. table 3 and table 4 present the relationship between the states of the m2, m1 and m0 input pins and the corresponding communication interface modes selected. this input pin (along with m0 and m2) is internally latched into the XRT4500 device, upon the rising edge of the latch signal. at this point, changes in this input pin will not effect the internally latched state of this pin. this input pin contains an internal 20k w pull-up to vdd.
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 5 pin descriptions (cont.) pin # signal dte mode dce mode type function 6m2 i mode control C mode select input 2 this input pin, along with m0 and m1 are used to configure the XRT4500 to operate in the desired communication interface mode. table 3 and table 4 present the relationship between the states of the m2, m1 and m0 input pins and the correspond- ing communication interface modes selected. this input pin (along with m0 and m1) is internally latched into the XRT4500 device, upon the rising edge of the latch sig- nal. at this point, changes in this input pin will not effect the internally latched state of this pin. this input pin contains an internal 20k w pull-up to vdd. 7 vss -6v power: this supply voltage is internally generated by the switching regulator circuit within the XRT4500. the -6v is used by tx 4, 5, 6, 7, 8. 8 tx4d d_rts d_cts i transmitter 4 C digital data input from terminal equipment the XRT4500 accepts binary ttl level data stream, via this input pin, converts it into either a v.10, v.11 or v.28 format and outputs it via the tx4a and tx4b output pins. the exact role that this pin plays depends upon whether the XRT4500 is operating in the dce or dte mode. dce mode C cts (clear to send) input if the XRT4500 is operating in the dce mode, then this input pin should be tied to the cts output pin of the terminal equipment. dte mode C rts (request to send) input if the XRT4500 is operating in the dte mode, then this input pin should be tied to the rts output pin of the terminal equipment. 9vdd analog vdd C for transmitters 4, 5, 6, 7 and 8 10 tx4b rtsb ctsb o transmitter 4 C positive data differential output to line the XRT4500 accepts a ttl binary data stream from the termi- nal equipment via the tx4d (pin 8) input pin. the XRT4500 will convert this data into either the v.10, v.11 or v.28 modes, and will output it via this pin and tx4a (pin 11). the exact role that this pin plays depends upon whether the XRT4500 is operating in the dte or dce mode. dte mode C positive polarity portion of rts line signal. dce mode C positive polarity portion of cts line signal. note: this output pin is not used if the XRT4500 has been con- figured to operate in either the v.28/eia-232 or v.10 modes.
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 6 pin descriptions (cont.) pin # signal dte mode dce mode type function 11 tx4a rtsa ctsa o transmitter 4 C negative data differential output to line the XRT4500 accepts a ttl binary data stream from the terminal equipment via the tx4d (pin 8) input pin. the XRT4500 will convert this data into either the v.10, v.11 or v.28 modes, and will output it via this pin and tx4b (pin 10). the exact function of this output pin depends upon whether the XRT4500 device is operating in the dte or dce mode. dte mode C negative polarity portion of the rts line signal. dce mode C negative polarity portion of the cts line signal. note: if the XRT4500 has been configured to operate in either the v.28/eia-232 or v.10 modes, then all of the data will be out- put (to the line) in a single-rail manner via this output pin. 12 tx5a dtra dsra o transmitter 5 C negative data differential output to line the XRT4500 accepts a ttl binary data stream via the tx5d (pin 15) input pin. the XRT4500 will convert this data into either the v.10, v.11 or v.28 modes, and will output it via this pin and tx5b (pin 13). the exact function of this output pin depends upon whether the XRT4500 device is operating in the dte or dce mode. dte mode C negative polarity portion of the dtr line signal. transmitter 5 accepts a ttl level binary data stream (as the data terminal read C dtr) from the terminal equipment. dce mode C negative polarity portion of the dsr line signal. note: if the XRT4500 has been configured to operate in either the v.28/eia-232 or v.10 modes, then all of the data will be out- put (to the line) in a single-rail manner via this output pin. 13 tx5b dtrb dsrb o transmitter 5 C positive data differential output to line the XRT4500 accepts a ttl binary data stream via the tx5d (pin 15) input pin. the XRT4500 will convert this data into either the v.10, v.11 or v.28 modes, and will output it via this pin and tx5a (pin 12). the exact function of this output pin depends upon whether the XRT4500 device is operating in the dte or dce mode. dte mode C positive polarity portion of dtr line signal. dce mode C positive polarity portion of dsr line signal. note: this output pin is not used if the XRT4500 has been con- figured to operate in either the v.28/eia-232 or v.10 modes. 14 gnd analog gnd C for transmitters 4, 5, 6, 7, and 8.
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 7 pin descriptions (cont.) pin # signal dte mode dce mode type function 15 tx5d d_dtr d_dsr i transmitter 5 C digital data input from terminal equipment this input pin accepts a ttl level binary data stream, from the local terminal equipment, and outputs it, in either a v.10, v.11 or v.28 manner, via the tx5a (pin 12) and tx5b (pin 13) output pins. the exact role that this input pin plays depends upon whether the XRT4500 is operating in the dte or dce modes. dte mode C data terminal ready (dtr) input pin if the XRT4500 is operating in the dte mode, then this input pin should be tied to the dtr output pin of the terminal equipment. dce mode C data set ready (dsr) input pin if the XRT4500 is operating in the dce mode, then this input pin should be tied to the dsr output pin of the terminal equipment. note: if the XRT4500 has been configured to operate in the registered mode, then data applied to this input pin will be latched (into the XRT4500) upon the rising edge of the reg_clk input signal. 16 vpp +12v power: this supply voltage is internally generated by the charge pump circuit within the XRT4500 device. if +12v is available, then the external components can be eliminated. 17 tx8d d_rl d_ri i transmitter 8 C digital data input from terminal equipment this input accepts a ttl level binary data stream, from the local terminal equipment, and outputs it, in either a v.10 or v.28 man- ner via the tx8o (pin 19) output pin. dce mode C ring indicator (or test mode) input pin if the XRT4500 has been configured to operate in the dce mode C this input pin should be connected to either the ri (ring indicator) or the tm (test mode) indicator output pin of the terminal equipment. dte mode C remote loop-back indicator input pin if the XRT4500 has been configured to operate in the dte mode C this input pin should be connected to the rl (remote loop-back) indicator output pin of the terminal equip- ment. note: if the XRT4500 has been configured to operate in the registered mode, then data applied to this input pin will be latched (into the XRT4500) upon the rising edge of the reg_clk input signal.
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 8 pin descriptions (cont.) n ote : signal names beginning with d_ are digital signals. n ote : signal names ending with b and a are the positive and negative polarities of differential signals respectively. pin # signal dte mode dce mode type function 18 lp i loopback command input pin C active low: this active-low input pin permits the user to configure the XRT4500 into a loop-back mode. the exact loop-back will depend upon whether the XRT4500 is operating in the dte or dce modes. setting this input pin to low enables the loop-back operation. setting this input pin to high disables the loop-back operation. this input pin contains an internal 20k w pull-up to vdd. 19 tx8o rla ria o transmitter 8 C single ended data output to line the XRT4500 accepts a ttl level binary data stream, from the local terminal equipment via the tx8d input pin (pin 17), and outputs it, in either a v.10 or v.28 manner via this output pin. the exact role that this output pin plays depends upon whether the XRT4500 is operating in the dte or dce modes. if the XRT4500 is configured to operate in the dce mode: this output pin will typically drive the state of either the ri (ring indicator) or tm (test mode) signals to the remote terminal equipment. if the XRT4500 is configured to operate in the dte mode: this output pin will typically drive the state of the rl (remote loop-back) signal to the remote terminal equipment. 20 vdd analog vdd C for receivers 4, 5, 6, 7 and 8. 21 cpp charge pump capacitor pin: a 2.2f tantalum capacitor must be connected between pin 21 and pin 22. 22 cpm charge pump capacitor pin: a 2.2f tantalum capacitor must be connected between pin 21 and pin 22.
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 9 pin descriptions (cont.) pin # signal dte mode dce mode type function 23 rx8d d_ri d_rl o receiver 8 C digital data output to terminal equipment the XRT4500 receives a line signal (in either the v.10 or v.28 manner) via the rx8i input pin (pin 25). the XRT4500 then con- verts this data into a digital format (e.g., a cmos level binary data stream) and outputs it via this pin. the exact functionality of this output pin depends upon whether the XRT4500 is operating in the dce or dte modes. dce mode C remote loop-back indicator output if the XRT4500 has been configured to operate in the dce mode C this output pin should be connected to the rl (remote loop-back) indicator input pin (of the terminal equipment). dte mode C ring indicator (or test mode indicator) output if the XRT4500 has been configured to operate in the dte mode C this output pin should be connected to either the ri (ring indicator) or tm (test mode) input pin of the terminal equipment. notes: this output pin is tri-stated if the en_out* input pin (pin 48) is high. if the XRT4500 has been configured to operate in the registered mode, then data will be outputted via this pin, upon the rising edge of the reg_clk clock signal. 24 reg i register mode control select input pin: this input pin permits the user to configure the XRT4500 to operate in either the registered mode or in the non-regis- tered mode. if the XRT4500 has been configured to operate in the registered mode, then the following will happen. ? data at the tx5d and tx8d input pins (pins 15 & 17) will be latched into the XRT4500 circuitry upon the rising edge of the clock signal applied at the reg_clk input pin. ? data will be output via the rx5d and rx8d pins, upon the rising edge of the clock signal applied at the reg_clk input pin. if the XRT4500 has been configured to operate in the non-reg- istered mode, then the reg_clk clock signal will have no effect on the processing of signals via the tx5d, tx8d, rx5d and rx8d pins. setting the reg input to high configures the XRT4500 to operate in the registered mode. setting the reg input to low configures the XRT4500 to operate in the non-registered mode. this pin contains an internal 20k w pull-down to ground.
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 10 pin descriptions (cont.) pin # signal dte mode dce mode type function 25 rx8i ria rla i receiver 8 C line input pin: this input pin accepts either a v.10 or v.28 type signal from the line. receiver 8 will then convert this signal into a cmos level (digital) signal and output this signal to the terminal equipment via the rx8d output pin (pin 23). the exact function of this out- put pin depends upon whether the XRT4500 device is operating in the dte or dce mode. dte mode C the ri line signal dce mode C the rl line signal notes : 1. for some dte applications, this input pin would accept the ri (ring indicator) line signal (in either the v.10 or v.28 format) form the dce terminal equipment. 2. for some dce applications, this input pin would accept the rl (remote loop-back) line signal (in either the v.10 or the v.28 format) from the dte terminal equipment. 26 vss -6v power: this supply voltage is internally generated by the switching regulator circuit within the XRT4500. the -6v is used by receivers 4, 5, 6, 7 and 8. if a -6v supply is available, then the external components can be eliminated. 27 tr7 lla lla i/0 transceiver # 7 i/o pins the exact function of this pin depends upon whether the XRT4500 is operating in the dce or dte modes. dte mode C transmitter 7 C single ended data output to line transceiver 7 accepts a cmos level signal via the tx76d input pin (pin 28). this digital data is converted into either a v.10 or v.28 electrical signal; which is then output (via this pin), on the line to the remote terminal equipment. dce mode C receiver 7 C single ended data input from line this input pin accepts the line signal, from the remote terminal equipment, in a single-ended manner. this line signal is con- verted into a cmos level signal and is output (to the local termi- nal equipment) via the rx67d output pin (pin 32). 28 tx76d d_ll d_dcd i digital input C refer to mode control tables, table 3 & table 4 .
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 11 pin descriptions (cont.) pin # signal dte mode dce mode type function 29 tr6a dcda dcda i/o transceiver # 6 line signal i/o pin: the exact function of this pin depends upon whether the XRT4500 has been configured to operate in the dce or dte mode. dte mode: negative polarity input of dcd (data carrier detect) signal: this input pin (along with tr6b, pin 30) accepts the line signal, from the remote terminal equipment, in either a single-ended or differential manner. this line signal is converted to cmos level signals and is outputted (to the local terminal equipment) via the rx67d output pin (pin 32). dce mode: negative polarity output signal (of dcd-data carrier detect) to the line: transceiver 6 accepts ttl level binary data stream, via the tx67d (pin 28) input pin. this output pin, along with tr6b (pin 30) will output this data to the remote terminal equipment). via an analog line signal. 30 tr6b dcdb dcdb i/o transceiver #6 line signal i/o pin the exact function of this pin, depends upon whether the XRT4500 has been configured to operate in the dce or dte mode. dte mode: receiver 6 C positive polarity input of dcd (data carrier detect) signal: this input pin (along with tr6a, pin 29) accepts the line signal, from the remote terminal equipment, in a differential manner. this line is converted to cmos signal levels and is output (to the local terminal equipment) via the rx67d output pin (pin 32). dce mode: transmitter 6 C positive polarity output of dcd (data carrier data signal) pin: transceiver 6 accepts a ttl level binary data stream, via the tx67d (pin 28) input pin. this output pin (along with tr6a, pin 29) will output this data (to the remote terminal equipment) via an analog line signal. n ote : this i/o pin is not used if the XRT4500 has been config- ured to operate in the v.28/eia-232 communications interface mode.
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 12 pin descriptions (cont.) n ote : signal names beginning with d_ are digital signals. n ote : signal names ending with b and a are the positive and negative polarities of differential signals respectively. pin # signal dte mode dce mode type function 31 dce/dte low high i dce/dte mode select: this input pin permits the user to configure the XRT4500 to operate in either the dce mode or in the dte mode. logic 0: dte mode operation when the XRT4500 is configured to operate in the dte mode, then transceiver # 3 will be configured to function as a receiver. logic 1: dce mode operation when the XRT4500 is configured to operate in the dce mode, then transceiver # 3 will be configured to function as a trans- mitter. this input pin contains an internal 20k w pull-up to vdd. 32 rx67d d_dcd d_ll o transceiver 6/7 digital output pin: the exact function of this pin depends upon whether the XRT4500 has been configured to operate in the dce or dte mode. dte mode C data carrier detect (dcd) output pin when the XRT4500 is operating in the dte mode, this trans- ceiver functions as a line receiver. this line receiver accepts either a v.10, v.28 or v.11 line signal via the tr6a and tr6b pins (pins 29 and 30) and converts this line signal into a cmos level binary data stream. this binary data stream is output via this pin. for dte applications, this output pin should be con- nected to the dcd input pin of the terminal equipment. dce mode C local loop-back (ll) indicator output pin when the XRT4500 is operating in the dce mode, this trans- ceiver functions as a line receiver. this line receiver accepts either a v.10, or v.28 line signal via the tr7 input pin (pin 27) and converts this line signal into a cmos level binary data stream. this binary data stream is output via this pin. for dce applications, this input pin should be connected to the ll input pin of the terminal equipment.
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 13 pin descriptions (cont.) n ote : signal names beginning with d_ are digital signals. n ote : signal names ending with b and a are the positive and negative polarities of differential signals respectively. pin # signal dte mode dce mode type function 33 rx5d d_dsr d_dtr o receiver 5 C digital data output to terminal equipment the XRT4500 accepts a line signal (in either the v.10, v.11 or v.28 manner) via the rx5a and rx5b input pins (pins 35 & 36). the XRT4500 then converts this data into digital format (e.g., a cmos level binary data stream) and outputs it to the terminal equipment via this pin. the exact role that this pin plays depends upon whether the XRT4500 device is operating in the dce or dte modes. dte mode C data set ready (dsr) output pin for dte applications, this output pin should be connected to the dsr input of the terminal equipment. dce mode C data terminal ready (dtr) output pin for dce applications, this output pin should be connected to the dtr input pin of the terminal equipment. note: 1. this output pin is tri-stated if the en_out input pin (pin 48) is high. 2. if the XRT4500 has been configured to operate in the registered mode, then data will be outputted via this pin upon the rising edge of the reg_clk clock signal. 34 ec i echo clock mode select input pin this input pin permits the user to enable or disable the echo- clock mode feature within the XRT4500 device. if the user con- figures the XRT4500 to operate in the echo-clock mode, then the rx3d output pin (pin 73) will be internally looped into the tx2d input pin (pin 67). setting this input pin low enables the echo-clock mode. setting this input pin high disables the echo-clock mode. note: the echo-clock mode feature is only available if the XRT4500 is operating in the dte mode. this input pin contains an internal 20k w pull-up to vdd.
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 14 pin descriptions (cont.) n ote : signal names beginning with d_ are digital signals. n ote : signal names ending with b and a are the positive and negative polarities of differential signals respectively. pin # signal dte mode dce mode type function 35 rx5b dsrb dtrb i receiver 5 C positive data differential input from line the XRT4500 will accept either a v.10, v.11 or v.28 type signal via this input pin, along with rx5a (pin 36) and will generate a result- ing cmos level binary data stream, via the rx5d (pin 33) output pin. the exact function of this input pin depends upon whether the XRT4500 device is operating in the dte or dce mode. dte mode C positive polarity portion of the dsr line signal. dce mode C positive polarity portion of the dtr line signal. note: this output pin is not used if the XRT4500 has been con- figured to operate in either the v.28/eia-232 or v.10 modes. 36 rx5a dsra dtra i receiver 5 C negative data differential input from line the XRT4500 will accept either a v.10, v.11 or v.28 type signal via this input pin, along with rx5b (pin 35) and will generate a resulting cmos level binary data stream, via the rx5d (pin 33) output pin. the exact function of this input pin depends upon whether the XRT4500 device is operating in the dte or dce mode. dte mode C negative polarity portion of the dsr line signal. dce mode C negative polarity portion of the dtr line signal. note: if the XRT4500 has been configured to operate in either the v.28/eia-232 or v.10 modes, then all of the data will be out- put (to the line) in a single-rail manner via this output pin. 37 rx4a ctsa rtsa i receiver 4 C negative data differential input from line the XRT4500 will accept either a v.10, v.11 or v.28 type signal via this input pin, along with rx4b (pin 38) and will generate a resulting cmos level binary data stream, via the rx4d output pin (pin 40). the exact function of this input pin depends upon whether the XRT4500 device is operating in the dte or dce mode. note: if the XRT4500 has been configured to operate in either the v.28/eia-232 or v.10 modes, then all of the data will be out- put (to the line) in a single-rail manner via this output pin. 38 rx4b ctsb rtsb i receiver 4 C positive data differential input from line the XRT4500 will accept either a v.10, v.11 or v.28 type signal via this input pin, along with rx4a (pin 37) and will generate a resulting cmos level binary data stream, via the rx4d output pin (pin 40). the exact function of this input pin depends upon whether the XRT4500 device is operating in the dte or dce mode. n ote : this output pin is not used if the XRT4500 has been con- figured to operate in either the v.28/eia-232 or v.10 modes.
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 15 pin descriptions (cont.) n ote : signal names beginning with d_ are digital signals. n ote : signal names ending with b and a are the positive and negative polarities of differential signals respectively. pin # signal dte mode dce mode type function 39 slew_cntl o v.28/v.10 slew-rate control pin C this pin permits the user to specify the slew rate of the v.10 or v.28 output driver. the user accompanies this by connecting a resistor (of a specific value) between this pin and ground. figure 34 presents a plot which depicts the relationship between the rise/fall time of a v.10 output signal (from the XRT4500) and the value of this resistor. figure 35 presents a plot which depicts the relationship between the slew-rate (expressed in terms of v/s) of a v.28 out- put signal (from the XRT4500) and the value of this resistor. 40 rx4d d_cts d_rts o receiver 4 C digital data output to terminal equipment this output pin is the digital (cmos level) representation of the line signal that is applied to the rx4a (pin 37) and rx4b (pin 38) input pins. the exact role that this pin plays depends upon whether the XRT4500 is operating in the dce or dte mode. dce mode C cts (clear to send) output signal for dce mode applications, this output pin should be connected to the cts input pin of the terminal equipment. dte mode C rts (request to send) output signal for dte mode applications, this output pin should be connected to the rts input pin of the terminal equipment. 41 vsense i switching regulator C voltage sense input 42 isense i switching regulator C current sense input 43 gnd_reg switching regulator ground 44 latch i mode control input latch enable C logic 0: this input pin permits the user to latch the states of the mode control input pins (4, 5, and 6) (m0, m1, and m2) into the XRT4500 circuitry. this feature frees up the signals (driving the mode control input pins) for other purposes. driving this input, from low to high latches the contents of the mode control pins of the XRT4500 (into the XRT4500 circuitry). for the duration that the latch input pin is high, the user can change the state of the signals controller the m0, m1 and m2 input pins, without effecting the operation of the XRT4500. 45 clkfs o internally generated 500khz clock C this clock signal is inter- nally used to drive both the switching regulator and the digital glitch filters. the user is advised to leave this pin floating.
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 16 pin descriptions (cont.) n ote : signal names beginning with d_ are digital signals. n ote : signal names ending with b and a are the positive and negative polarities of differential signals respectively. pin # signal dte mode dce mode type function 46 e_232h i high speed rs-232 enable C logic 0 enables high speed rs- 232 mode (drives 3k w in parallel with 1000pf at 256 khz). internal 20k w pull-up to vdd. this input pin permits the user to either enable or disable the high-speed rs-232 driver feature. the non high speed mode provides a 120 kbps clock rate. note: this pin setting applies to all rs-232/v.28 drivers within the XRT4500. 47 v dd analog vdd for the internal switching regulator 48 en_out i output enable pin for receiver 5 and 8 this active-low output pin permits the user to tri-state the rx5d and rx8d output pins (pins 23 & 33). setting this input pin low causes the XRT4500 to tri-state the rx5d and rx8d output pins. conversely, setting this input pin high enables the rx5d and the rx8d output drivers for signal transmission to the local terminal equipment. this input pin contains an internal 20k w pull-down resistor to ground. 49 reg_clk i register mode clock input signal: if the XRT4500 has been configured to operate in the regis- tered mode, then a rising clock edge at this input causes the XRT4500 to do the following. ? data at the tx5d and tx8d input pins (pins 15 & 17) will be latched into the XRT4500 circuitry. ? data will be outputted via the rx5d and rx8d pins (pins 23 & 33). this input pin has no function when the XRT4500 is operating in the non-registered mode. the user configures the XRT4500 to operate in the registered mode, by pulling the reg input pin to v dd . this input pin contains an internal 20k w pull-up to v dd .
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 17 pin descriptions (cont.) n ote : signal names beginning with d_ are digital signals. n ote : signal names ending with b and a are the positive and negative polarities of differential signals respectively. pin # signal dte mode dce mode type function 50 2ck/3ck i 2 or 3 clock select input pin this input pin permits the XRT4500 to operate in either the 2 clock or 3 clock mode. if the XRT4500 is configured to oper- ate in the 2-clock mode, then the XRT4500 will synthesize the rx2d clock signal, from the clock signal applied at the tx3d input pin. conversely, if the XRT4500 is configured to operate in the 3 clock mode, then the XRT4500 will synthesize the rx2d clock signal from the live signal received via rx2a and rx2b input pin. setting this input pin high configures the XRT4500 to operate in the 2 clock mode. conversely, setting this input pin low configures the XRT4500 to operate in the 3 clock mode. note: 1. this input pin is ignored if the XRT4500 is configured to support the x.21 communications interface. logic dont care: 1 clock when in the x.21 mode (m2, m1, m0 = 011) logic 0: 3 clocks when mode 1 x.21 (m2, m1, m0 1 011) logic 1: 2 clocks when mode 1 x.21 (m2, m1, m0 1 011) n ote : 2. this input pin is ignored if the XRT4500 is configured to operate in the dte mode. this input pin contains an internal 20k w pull-up to v dd . 51 vdd_reg analog vdd C charge pump and switching regulator output drivers 52 sr_out o switching regulator C inductor driver output
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 18 pin descriptions (cont.) pin # signal dte mode dce mode type function 53 oscen i test oscillator enable C active low; this active-low input pin permits the user to enable or disable the internal oscillator within the XRT4500. if the user enables this fea- ture then the XRT4500 will begin generating a clock signal via both the rx2d and rx3d output pins. the frequency of this clock signal ranges between 32khz and 64khz. this clock signal can be used to support stand-alone dte diag- nostic testing. setting this input to 0 enables the internal oscillator. setting this input to 1 disables the internal oscillator. note: the internal oscillator is only available if the XRT4500 is operating in the dte mode. if lp = 0 the clock signal (32 - 64khz) is available on rx3d. if lp = 0 and ec = 0 the clock signal is available on rx2d. n ote : this input pin contains an internal 20k w pull-up to v dd . 54 clkinv i invert clock input pin C this active -low input pin permits the user to either enable or disable the clock/inversion feature. the exact manifestation of the clock inversion feature depends upon whether the XRT4500 is operating in the dce or dte mode. if the XRT4500 is operating in the dte mode, then the rx3d output signal (which is receiving the txc signal) will be inverted before it is outputted to the terminal equipment. if the XRT4500 is operating in the dce mode, then the tx3d input signal (which is transmitting the txc signal) will be inverted before it converted into the analog format and is output to the line. setting this input pin low enables the clock inversion feature. conversely, setting this input pin high disables this feature. n ote : this input pin contains an internal 20k w pull-up to v dd . 55 dtinv i invert data C active low ; logic 0: data inverted. logic 1: data not inverted. internal 20k w pull-up v dd . 56 vss_t123 -6v power supply signal: this supply voltage is internally gener- ated by the switching regulator circuit within the XRT4500. 57 gnd digital ground: for transmitters 1, 2, and 3 58 vdd_t123 analog vdd: for transmitters 1, 2, and 3 59 gnd_t12 analog ground: transmitters 1 and 2
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 19 pin descriptions (cont.) pin # signal dte mode dce mode type function 60 tx1d d_txd d_rxd i transmitter 1 C digital data input from terminal equipment . the exact role that this input pin plays depends upon whether the XRT4500 is operating in the dte or dce modes. dte mode C txd (transmit data) input: the dte terminal equipment is expected to apply the txd (transmit data) to this input pin. the XRT4500 will convert this binary data stream into either the v.35, v.11, or v.28 format and will output this data via the tx1a and tx1b output pin. dce mode C rxd (receive data) input: the dce terminal equipment is expected to apply the rxd (receive data) to this input pin. the XRT4500 will convert this binary data stream into either the v.35, v.11 or v.28 format and will output this data via the tx1a and tx1b output pins. 61 cm_tx1 o ac gnd- transmitter 1 output termination center tap in v.35 mode. connect a 0.1f capacitor to ground. 62 tx1b txdb rxdb o transmitter 1 C positive data differential output to line . the exact function of this output pin depends upon whether the XRT4500 is operating in the dce or dte modes. dte mode: transmit data (txd) C positive polarity output line signal transmitter 1 accepts a ttl level binary data stream (as the transmit data C txd) from the dte terminal equipment. transmitter 1 converts this digital data into any of the following electrical formats: v.10, v.11, v.28 and v.35, prior to transmis- sion to the line. if this data is being converted into either the v.11 or v.35 format, then this pin outputs the positive-polarity portion of the txd data to the line. if this data is being converted into either the v.10 or v.28 formats, then this pin is inactive. dce mode: receive data (rxd) C positive polarity output line signal transmitter 1 accepts a cmos (or ttl) level signal binary data stream (as the receive data C rxd) from the dce terminal equipment. transmitter 1 converts this digital data into any of the following electrical formats: v.10, v.11, v.28 and v.35 prior to transmission to the line. if this data is being converted into either the v.11 or v.35 format, then this pin outputs the positive polarity portion of the rxd data to the line. if this data is being converted into either the v.10 or v.28 formats, then this pin is inactive.
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 20 pin descriptions (cont.) pin # signal dte mode dce mode type function 63 tx1a txda rxda o transmitter 1 C negative data differential output to line the exact function of this output pin depends upon whether the XRT4500 is operating in the dce or dte modes. dte mode: transmit data (txd) C negative polarity output signal transmitter 1 accepts a ttl level binary data stream (as the transmit data C txd) from the dte terminal equipment. trans- mitter 1 converts this digital data into any of the following electrical formats: v.10, v.11, v.28 and v.35 prior to transmission to the line. if this data is being converted into either the v.11 or v.35 format, then this pin outputs the negative-polarity portion of the txd data to the line. if this data is being converted into either the v.10 or v.28 formats, then this pin outputs this data to the line in a sin- gle-ended manner. dce mode: receive data (rxd) C negative polarity output line signal transmitter 1 accepts a ttl level binary data stream (as the receive data C rxd) from the dce terminal equipment. transmitter 1 converts this digital data into any of the following electrical formats: v.10, v.11, v.28 and v.35 prior to transmission to the line. if this data is being converted into either the v.11 or v.35 format, then this pin outputs the negative-polarity portion of the rxd data to the line. if this data is being converted into either the v.10 or v.28 formats, then this pin outputs this data to the line in a sin- gle-ended manner.
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 21 pin descriptions (cont.) pin # signal dte mode dce mode type function 64 tx2a sctea rxca o transmitter 2 C negative data differential output to line the exact function of this output pin depends upon whether the XRT4500 is operating in the dce or dte mode. dte mode transmit clock echo (scte) C negative polarity output signal transmitter 2 accepts a ttl level binary data system (as the transmit clock echo C scte) from the dte terminal equip- ment. transmitter 2 converts this digital data into any of the fol- lowing electrical formats: v.10, v.11, v.28 or v.35 prior to transmission to the line. if this data is being converted into the v.11 or v.35 electrical format then this pin outputs the negative polarity portion of the scte data to the line. if this data is being converted into the v.10 or v.28 electrical format, tthen this pin outputs this data to the line in a single-ended manner. dce mode receive clock (rxc) signal C negative polarity output line signal transmitter 2 accepts a ttl level binary data system (as the receive clock - rxc) from the dce terminal equipment. trans- mitter 2 converts this digital data into any of the following electrical formats: v.10, v.11, v.28 or v.35 prior to transmission to the line . if this data is being converted into the v.11 or v.35 electrical for- mat then this pin outputs the negative polarity portion of the rxc data to the line. if this data is being converted into the v.10 or v.28 electrical format, then this pin outputs this data to the line in a single-ended manner.
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 22 65 tx2b scteb rxcb o transmitter 2 C positive data differential output to line. the exact function of this output pin depends upon whether the XRT4500 is operating in the dce or dte mode. dte mode transmit clock echo (scte) C positive polarity output signal transmitter 2 accepts a ttl level binary data system (as the transmit clock echo C scte) from the dte terminal equip- ment. transmitter 2 converts this digital data into any of the fol- lowing electrical formats: v10, v.11, v.28 or v.35 prior to transmission to the line. if this data is being converted into the v.11 or v.35 electrical format then this pin outputs the positive polarity portion of the scte data to the line. if this data is being converted into the v.10 or v.28 electrical format, then this output pin is in-active. dce mode receive clock (rxc) signal C positive polarity output line signal transmitter 2 accepts a ttl level binary data system (as the receive clock - rxc) from the dce terminal equipment. trans- mitter 2 converts this digital data into any of the following electrical formats: v.10, v.11, v.28 or v.35 prior to transmission to the line . if this data is being converted into the v.11 or v.35 electrical for- mat then this pin outputs the positive polarity portion of the rxc data to the line. if this data is being converted into the v.10 or v.28 electrical format, then this output pin is in-active. 66 cm_tx2 o transmitter 2 output termination center tap in v.35 mode C this pin should be by-passed to ground with an external 0.1f capacitor. pin # signal dte mode dce mode type function
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 23 pin descriptions (cont.) pin # signal dte mode dce mode type function 67 tx2d d_scte d_rxc i transmitter 2 C digital data input from terminal equipment the exact role that this input pin plays, depends upon whether the XRT4500 is operating in the dte or dce mode. dte mode: scte (transmit clock echo) input the serial communications controller (at the dte terminal) is expected to derive the scte (transmit clock echo) clock signal, from the txc signal, and input it (into the XRT4500) via this input pin. the XRT4500 will convert this binary data stream into either the v.35, v.11 or v.28 format and will output this data via the tx2a and tx2b output pins. dce mode: rxc (receive clock) input the serial communications controller (at the dce terminal) is expected to apply the rxc clock signal to this input pin. the XRT4500 will convert this binary data stream into either the v.35, v.11 or v.28 format and will output this data via the tx2a and tx2b output pins. note: if the XRT4500 has been configured to operate in both the dte and the echoed clock mode, then the XRT4500 will ignore this input pin and will instead use the clock signal which is output via the d_txc output pin (e.g., rx3d or pin 73). 68 tx3d d_x d_txc i transmitter 3 C digital data input from terminal equipment the exact role that this pin plays depends upon whether the XRT4500 is operating in the dce or dte modes. dte mode: this input pin is not used dce mode: txc C transmit clock signal this input pin functions as the txc (transmit clock) input signal from the dce terminal. the XRT4500 will convert this digital clock data into either the v.35, v.11 or v.28 format and will output this data via the tr3a and tr3b output pins. 69 cm_tr3 o dte mode: ac gnd C transmitter 3 output termination center tap in v.35 mode. connect a 0.1f capacitor to ground. dce mode: ac gnd C receiver 3 input termination center tap in v.35 mode. connect a 0.1f capacitor to ground. 70 tr3a txca txca i/o dte mode: receiver 3 C negative data differential input from line dce mode: transmitter 3 C negative data differential output to line. 71 tr3b txcb txcb i/o dce mode: transmitter 3 C positive data differential output to line. dte mode: receiver 3 C positive data differential input from line.
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 24 pin descriptions (cont.) pin # signal dte mode dce mode type function 72 gnd analog gnd: receivers 4, 5, 6, 7 and 8 73 rx3d d_txc d_x o receiver 3 C digital output to terminal equipment: this output pin is the digital (cmos level) representation of the line signal that is received via the tr3a (pin 70) and tr3b (pin 71) input pins. the exact role that this pin plays depends upon whether the XRT4500 is operating in the dce or dte mode. dte mode: txc C transmit clock signal this output pin functions as the txc (transmit clock) output signal to the terminal equipment. the dte terminal equipment will typically use this signal to synthesize the scte clock signal. dce mode: this output pin is not used. note: if the internal oscillator (within the XRT4500) is enabled, then this pin will output a 32khz to 64khz clock signal. this clock signal can be used for stand-alone dte diagnostic testing. 74 rx2d r_rxc d_scte o receiver 2 C digital data output to equipment this output pin is the digital (cmos level) representation of the line signal that is received via the rx2a (pin 77) and rx2b (pin 76) input pins. the exact role that this pin plays depends upon whether the XRT4500 is operating in the dce or dte modes. dce mode: scte C transmit clock echo signal: this output pin functions as the scte (transmit clock echo) output signal to the terminal equipment. the dce terminal equipment will typically use this clock signal to sample the txd (transmit data). dte mode: rxc C receive clock signal: this output pin functions as the rxc (receive clock) output signal to the terminal equipment. the dte terminal equipment will typically use this signal to sample the rxd (receive data). note: if the internal oscillator (within the XRT4500) is enabled, then this pin will output a 32khz C 64khz clock signal. this clock signal can be used for stand-alone dte diagnostic testing. 75 en_fltr i enable glitch filter on receiver 4, 5, 6, 7, 8 inputs. internal 20k w pull-down 76 rx2b rxcb scteb i receiver 2 C positive data differential input from line 77 rx2a rxca rxcb i receiver 2 C negative data differential input from line
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 25 pin descriptions pin # signal dte mode dce mode type function 78 rx1a rxda txda i receiver 1 C negative data differential input from line 79 rx1b rxdb txdb i receiver 1 C positive data differential input from line the exact function of this input pin depends upon whether the XRT4500 is operating in the dce or dte mode. this input pin, along with rx1a (pin 78) will accept a line signal in either the v.35, v.11, v.28/eia-232 or v.10 electrical format. receiver 1 will then convert this line signal into a cmos level binary data stream, and will output this data (to the terminal equipment) via the rx1d output pin (pin 1). dce mode C receive data (rxd) C negative polarity input line signal 80 en_term i enable input termination for receiver 1, 2, 3, in v.11 mode. internal 20k w pull-down to ground.
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 26 electrical characteristics n otes : 1. absolute maximum ratings are those beyond which the safety of a device may be impaired. 2. all currents into device pins are positive; all cur- rents out of device are negative. all voltages are referenced to device ground unless otherwise specified. 3. the efficiency of the switching regulator and the charge pump is approximately 70%. the actual power dissipation of the XRT4500 at 5v, with maxi- mum loading, is 660mw in v.10, 700mw in v.11, 950mw in v.35 and 800mw in the v.28 mode. in the reduced power mode the XRT4500 chip dis- sipation is 310mw. 4. "typical load" is the corresponding receiver in another XRT4500 operating in the dte mode. 5. a 50% duty cycle square wave, at the specified fre- quency in the table, is applied to all clock and data lines of the high speed transmitters). 6. a 10 khz 50% duty cycle square wave is applied to all handshake lines (low speed transmitters). supply voltage m in t yp m ax units t est c onditions vpp +12v supply 11 12 13 v full load on v.28 vss -5.7 -6.0 -6.3 v full load on v.28 idd in dce mode- ta=25c, vdd=5v, data and clock at maximum operating frequencies unless other- wise specified p arameter m in t yp m ax units t est c onditions v. 1 0 m0=0, m1=0, m2=0 145 160 180 160 180 200 190 215 240 ma no load or signal, tx digital inputs tied high typical load at 10 khz typical load at 50 khz eia-530-a (v.11) m0=1, m1=0, m2=0 125 205 230 275 140 230 255 305 170 275 305 365 ma no load or signal, tx digital inputs tied high typical load at 1 mhz typical load at 4 mhz typical load at 10 mhz eia-530, rs449, v.36 m0=0, m1=1, m2=0 120 195 225 270 135 215 250 300 160 260 300 360 ma no load or signal, tx digital inputs tied high typical load at 1 mhz typical load at 4 mhz typical load at 10 mhz x.21 m0=1, m1=1, m2=0 115 195 215 260 130 215 240 290 155 260 290 350 ma no load or signal, tx digital inputs tied high typical load at 1 mhz typical load at 4 mhz typical load at 10 mhz v. 3 5 m0=0, m1=0, m2=1 215 255 265 290 240 285 295 320 290 340 355 385 ma no load or signal, tx digital inputs tied high typical load at 1 mhz typical load at 4 mhz typical load at 10 mhz reserved m0=1, m1=0, m2=1 120 200 225 270 135 225 250 300 160 270 300 360 ma no load or signal, tx digital inputs tied high typical load at 1 mhz typical load at 4 mhz typical load at 10 mhz rs-232 (v.28) m0=0, m1=1, m2=1 115 215 225 130 240 250 155 290 300 ma no load or signal, tx digital inputs tied high typical load at 10 khz typical load at 100 khz power down m0=1, m1=1, m2=1 80 90 110 ma reduced power mode
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 27 7. input termination is enabled on high speed v.11 receivers. n otes : 1. absolute maximum ratings are those beyond which the safety of a device may be impaired. 2. all currents into device pins are positive; all cur- rents out of device are negative. all voltages are referenced to device ground unless otherwise specified. 3. the efficiency of the switching regulator and the charge pump is approximately 70%. the actual power dissipation of the XRT4500 at 5v, with maxi- mum loading, is 660mw in v.10, 700mw in v.11, 950mw in v.35 and 800mw in the v.28 mode. in the reduced power mode the XRT4500 chip dis- sipation is 310mw. 4. "typical load" is the corresponding receiver in another XRT4500 operating in the dce mode. 5. a 50% duty cycle square wave, at the specified fre- quency in the table, is applied to all clock and data lines of the high speed transmitters). 6. a 10 khz 50% duty cycle square wave is applied to all handshake lines (low speed transmitters). 7. input termination is enabled on high speed v.11 receivers. idd in dte mode - ta=25c, vdd=5v, data and clock at maximum operating frequencies unless other- wise specified p arameter m in t yp m ax units t est c onditions v. 1 0 m0=0, m1=0, m2=0 145 160 170 160 180 190 190 215 230 ma no load or signal, tx digital inputs tied high typical load at 10 khz typical load at 50 khz eia-530-a (v.11) m0=1, m1=0, m2=0 130 190 210 250 145 210 235 280 175 250 280 335 ma no load or signal, tx digital inputs tied high typical load at 1 mhz typical load at 4 mhz typical load at 10 mhz eia-530, rs449, v.36 m0=0, m1=1, m2=0 125 180 205 245 140 200 230 275 170 240 275 330 ma no load or signal, tx digital inputs tied high typical load at 1 mhz typical load at 4 mhz typical load at 10 mhz x.21 m0=1, m1=1, m2=0 120 170 190 230 130 190 210 255 155 230 250 305 ma no load or signal, tx digital inputs tied high typical load at 1 mhz typical load at 4 mhz typical load at 10 mhz v. 3 5 m0=0, m1=0, m2=1 180 220 235 255 200 245 260 285 240 295 310 340 ma no load or signal, tx digital inputs tied high typical load at 1 mhz typical load at 4 mhz typical load at 10 mhz reserved m0=1, m1=0, m2=1 125 185 205 245 140 205 230 275 170 245 275 330 ma no load or signal, tx digital inputs tied high typical load at 1 mhz typical load at 4 mhz typical load at 10 mhz rs-232 (v.28) m0=0, m1=1, m2=1 115 200 205 130 220 230 155 265 275 ma no load or signal, tx digital inputs tied high typical load at 10 khz typical load at 100 khz power down m0=1, m1=1, m2=1 80 90 110 ma reduced power mode
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 28 ta = 25c, vdd = 5v, vss = -6v, vpp = 12v, m aximum o perating f requency u nless o therwise s pecified s ymbol p arameter m in t yp m ax u nits m ode i nterface /c onditions s upply c urrents m0 m1 m2 t est c onditions i dd v dd supply current (dce mode, all digital pins = gnd or v dd ) 27 32 ma 0 0 0 v.10, no load, no signal 75 90 ma 0 0 0 v.10, full load, w/ signal 27 32 ma 1 0 0 eia-530a, no load, (v.11) 230 270 ma 1 0 0 eia-530a, full load, (v.11) 65 75 ma 0 0 1 v.35, no load on v.28 drivers 68 80 ma 0 0 1 v.35, full load on v.28 drivers 20 25 ma 0 1 1 rs232, no load 26 32 ma 0 1 1 rs232, full load 16 20 ma 1 1 1 reduced power mode e lectrical c haracteristics (c ontiued ) s ymbol p arameter m in t yp m ax u nit c onditions l ogic i nputs vih logic input high voltage 2 v ttl compatible v il logic input low voltage 0.8 v ttl compatible i in logic input current 250 m awith 20k w internal pull-up/down resistor to ground l ogic o utputs v oh output high voltage 3 4.5 v i o = -4ma, ttl/cmos compatible v ol output low voltage 0.3 0.8 v i o = 4ma, ttl/cmos compatible i osr output short-circuit current -60 60 ma 0v v o v dd , ttl compatible i ozr three-state output current 0 1 m a m0 = ml = m2 = v dd 0v v o v dd , ttl compatible
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 29 p ower s upply c onsumption when external power supplies are available, the switching regulator and charge pumps may be dis- abled to save on component cost and current con- sumption from the +5v supply. the table below shows the typical currents the +5v, +12v and -6v supplies require for each of the interface modes. the following two charts show how the idd current varies with temperature and voltage when only a sin- gle 5v supply is used in the eia-530 (v.11) mode. this mode has the highest current consumption. i dd i pp i ss m ode i nterface /c onditions s upply +5v +12v -6v u nit m2 m1 m0 27 17 40 ma 0 0 0 v.10, no load, no signal 75 17 -160 ma 0 0 0 v.10, full load with signal 27 15 -35 ma 0 0 1 eia-530a, no load (v.11) 230 15 -130 ma 0 0 1 eia-530a, full load (v.11) 27 15 -35 ma 0 1 0 eia-530 (v.36) no load 27 15 -35 ma 0 1 1 x.21 65 15 -70 ma 1 0 0 v.35, no load on v.28 drivers 68 45 -120 ma 1 0 0 v.35, full load on v.28 drivers 27 15 -35 ma 1 0 1 reserved 20 30 -45 ma 1 1 0 rs-232, no load 26 65 -55 ma 1 1 0 rs-232, full load f igure 1. s upply c urrent versus t emperature and s upply v oltage , without l oad or s ignal in eia-530 (v.11) mode supply current, no signal, no load, all ch 140 142 144 146 148 150 152 154 - 200 25507085 temperature ( c) idd (ma) 4.75v 5.00v 5.25v
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 30 f igure 2. s upply c urrent versus t emperature and s upply v oltage , with l oad in eia- 530 (v.11) mode supply current, signal, full load 310 320 330 340 350 360 - 20 0 25 50 70 85 temperature (c) idd (ma) 4.75v 5.00v 5.25v e lectrical c haracteristics (c ontiued ) s ymbol p arameter m in t yp m ax u nit c onditions v. 1 1 d river v od differential output voltage + 5.5 v open circuit v od differential output voltage 2 r l = 50 w (figure 3) d v od change in magnitude of differential output voltage 0.25 v r l = 50 w (figure 3) v oc common mode output voltage 3.0 v r l = 50 w (figure 3) d v oc change in magnitude of common mode output voltage 0.2 v r l = 50 w (figure 3) i ss short-circuit current 150 ma v o = gnd i oz output leakage current 1 100 m a-0.25v v o 0.25v, power off or driver disabled t r , t f rise or fall time (transition time) 4 10 25 ns (figures 4, 8 ) t plh input to output 30 70 100 ns (figures 4, 8 ) t phl input to output 30 65 100 ns (figures 4, 8 ) d t inp. to out. difference, |t plh - t phl | 0 5 15 ns (figures 4, 8 ) t skew output to output skew 5 ns (figures 4, 8 ) v. 1 1 r eceiver maximum transmission rate 20 mhz v th input threshold voltage -0.2 0.2 v -7v v cm 7v d v th input hysteresis 35 60 mv -7v v cm 7v
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 31 v. 1 1 r eceiver i in input current (a, b) 2 2.5 ma -10v v a,b 10v r in input impedance 9 10 11 k w -10v v a,b 10v t r , risetime 10 ns (figures 4, 9 ) t f fall time 5 10 ns (figures 4, 9 ) t plh input to output 30 70 100 ns (figures 4, 9 ) t phl input to output 30 70 100 ns (figures 4, 9 ) d t inp. to out. difference, |t plh - t phl | 0 10 20 ns (figures 4, 9 ) e lectrical c haracteristics (c ontiued ) s ymbol p arameter m in t yp m ax u nit c onditions e lectrical c haracteristics (c ontinued ) s ymbol p arameter m in t yp m ax u nit c onditions v.35 driver maximum transmission rate 20 mhz v od differential output voltage 0.44 0.55 0.66 v with load, (figure 9) i oh transmitter output high current -12 -11 -10 ma v a, b = 0v i ol transmitter output low current 10 11 12 ma v a, b = 0v i oz transmitter output leakage current 1 100 m a-0.25 v a,b 0.25v t r , t f rise or fall time 5 ns (figures 5, 8 ) t plh input to output 30 60 100 ns (figures 5, 8 ) t phl input to output 25 55 80 ns (figures 5, 8 ) d t inp. to out. difference, |t plh - t phl | 0 5 20 ns (figures 5, 8 ) t skew output to output skew 5 ns (figures 5, 8 ) v.35 receiver v th differential input threshold volt. -0.2 0.2 v -2v = (v a + v b )/2 = 2v (figure 5) d v th input hysteresis 35 60 mv -2v = (v a + v b )/2 = 2v (figure 5) i in input current (a, b) 60 ma -10v = v a, b = 10v r in input impedance (a, b) 135 150 165 w -10v = v a, b = 10v t r rise time 10 ns (figure 5, 9 ) t f fall time 5 ns (figure 5, 9 ) t plh input to output 75 100 ns (figure 5, 9 ) t phl input to output 75 100 ns (figure 5, 9 )
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 32 e lectrical c haracteristics - t a = 25c, v dd = 5v + 5% s ymbol p arameter m in t yp m ax u nit c onditions v. 1 0 driver maximum transmission rate 120 kbps v o output voltage 4.0 6.0 v open circuit, r l = 3.9k v o output voltage 3.6 v r l = 450 w (figure 6) i ss short-circuit current 100 ma v o = gnd i oz input leakage current 0.1 100 m a-0.25 v o 0.25v, power off or driver disabled t r , t f rise or fall time 0 1.5 m s (figures 6, 10 ), r l = 450 w , c l = 100pf, r slew_cntl = 10k t plh input to output 1.5 3 6 m s ( figures 6, 10 ) , r l = 450 w , c l = 100pf r slew_cntl = 10k t phl input to output 0.5 1 2 m s ( figures 6, 10 ) , r l = 450 w , c l = 100pf r slew_cntl = 10k v. 1 0 r eceiver v th receiver input threshold voltage -0.2 0.2 v a vth receiver input hysteresis 35 60 mv i in receiver input current -2.5 2.0 2.5 ma -10 v a 10v r in receiver input impedance 9 11 12 k w -10 v a 10v t r , t f rise or fall time 10 ns (figures 7, 11 ) t plh input to output 200 ns (figures 7, 11 ) t phl input to output 250 ns (figures 7, 11 ) v.28 driver maximum transmission rate 120 kbps v o output voltage 5 5.5 6.5 v open circuit rl = 3k (figure 6) i ss short-circuit current 100 ma v o = gnd i oz input leakage current 1 100 m a-0.25 v cm 0.25v, power off or driver disabled sr slew rate 2 5 30 v/ m s (figures 6, 10 ), r l = 3k, c l = 2500pf t plh input to output 2 6 m s (figures 6, 10 ), r l = 3k, c l = 2500pf t phl input to output 2 6 m s (figures 6, 10 ), r l = 3k, c l = 2500pf
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 33 the following tests circuits and timing diagrams are referenced in the preceding electrical characteristics ta b l e s . e lectrical c haracteristics (c ontinued ) s ymbol p arameter m in t yp m ax u nit c onditions v. 2 8 r eceiver maximum transmission rate 256 kbps v thl input low threshold voltage 1.4 0.8 v v tlh input high threshold voltage 2.0 1.4 v a vth receiver input hysteresis 0.1 0.4 1.0 v r in receiver input impedance 3 5 7 k w -15 v a 15v t r , t f rise or fall time 10 ns (figures 7, 11 ) t plh input to output 400 ns (figures 7, 11 ) t phl input to output 450 ns (figures 7, 11 ) f igure 3. rs422 d river t est c ircuit rl=50 w rl=50 w voc txa txb vod f igure 4. rs422 d river /r eceiver ac t est c ircuit
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 34 f igure 5. v.35 d river /r eceiver ac t est c ircuit (tx1/rx1, tx2/rx2 o nly ) f igure 6. v.10/v.28 d river t est c ircuit f igure 7. v.10 (rs-423) v.28 (rs-232) r eceiver t est c ircuit f igure 8. v.11, v.35 d river p ropagation d elays f igure 9. v.11, v.35 r eceiver p ropagation d elays v1 = 0v for v.35, 2.5v for v.11
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 35 n otes : 1. 7 v on receivers 1-6, not applicable for receiv- ers 7-8 2. 100 to 150 ohms terminated. f igure 10. v.10 (rs-423) v.28 (rs-232) d river p ropagation d elays f igure 11. v.10, v.28 r eceiver p ropagation d elays v1 = 1.8v for v.28, 0.1v for v.10 v2 = 1.0v for v.28. -0.1v for v.10 t able 1: r eceiver s pecifications s ingle -e nded or d ifferential v. 3 5 d ifferential v. 1 1 d ifferential v. 1 0 s ingle -e nded rs232 s ingle -e nded max signal level 660 mv 6 v 6 v 15 v min signal level 260 mv 300 mv 300 mv 3 v common-mode voltage 2 v 7 v note 1 n/a max signal peak operation 2.66 v 10 v 10 v 15 v max signal peak no damage 10 v 12 v 12 v 25 v rin differential 100 w 10% note 2 n/a n/a rin common-mode 150 w 15% n/a n/a n/a dc rin each input to ground > 175 w > 8k w > 8k w 3k w < dc rin < 7 k w clock frequency 20 mhz 20mhz 120khz 256khz
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 36 t able 2: t ransmitter s pecification s ingle -e nded or d ifferential v. 3 5 d ifferential v. 1 1 d ifferential v. 1 0 s ingle -e nded rs-232 s ingle -e nded max signal level 660 mv rl = 100 w |v0| < 6 v rl = 3900 w 4 < |v0| < 6 v rl = 3900 w 6 v 3000 w < rl < 7000 w min signal level 440 mv rl = 100 w 2v < |vt| >0.5 v0 r l = 100 w |vt| > 0.9 v0 rl = 450 w 5 v 3000 w < rl < 7000 w offset voltage n/a |vos| < 3v n/a n/a rout differential 100 w 10% 100 w n/a n/a rout common-mode 150 w 15% n/a n/a n/a rout power off n/a n/a n/a > 300 w output slew rate/tr,tf 20 ns 20 ns 1ms < 30 v/ms clock frequency 20 mhz 20 mhz 120 khz 256 khz
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 37 1.0 system description the XRT4500 multi-protocol serial network interface ic is a flexible transceiver chip that is capable of sup- porting the following communication interfaces. ? itu-t v.35 ? itu-t v.28/eia-232 ? eia-449 ? itu-t v.36 ? itu-t x.21 ? eia-530 ? eia-530a the XRT4500 uses the following electrical interfac- es in order to realize each of these communication interfaces. ? itu-t v.11/eia-422 ? itu-t v.10/eia-423 ? itu-t v.35 ? itu-t v.28/eia-232 1.1 the difference between an electri- cal interface and a communications interface it is important to describe the difference between an electrical interface specification and a communica- tions interface specification. an electrical interface specification defines the electrical characteristics of a transmitter or receiver. these characteristics include voltage, current, impedance levels, rise/fall times and other similar parameters. examples of electrical inter- faces are itu-t v.10 (eia-423), itu-t v.11 (eia- 422), v.35 and v.28 (eia-232). in contrast, a communications interface specification describes a physical layer interface in its entirety. this description includes the names and functions of all of the involved signals. the communications inter- face specification identifies which electrical interface is to be used to realize each of these signals as well as the connector type. examples of communication interface types include itu-t v.35, itu-t v.28 (eia- 232), eia-449, eia-530a, itu-t x.21, and itu-t v. 3 6 . for example, the itu-t v.35 communications inter- face specification requires that each of the following signals must comply with the itu-t v.35 electrical interface requirements. ? rxd - receive data (ccitt circuit 104) ? txd - transmit data (ccitt circuit 103) ? rxc - receive clock (ccitt circuit 115) ? txc - transmit clock (ccitt circuit 114) ? scte (or txce) - transmit clock echo also, the itu-t v.35 communications interface speci- fication states that each of the following signals must comply with the itu-t v.28 electrical interface re- quirements. ? rts - request to send (ccitt circuit 105) ? cts - clear to send (ccitt circuit 106) ? dtr - data terminal ready ? dsr - data set ready (ccitt circuit 107) ? dcd - data carrier detect (ccitt circuit 109) ? rl - remote loop-back indicator* ? ll - local loop-back indicator* ? tm - test mode indicator* n ote : *option signals, per the itu-t v.35 electrical interface finally, the itu-t v.35 communications interface recommends the use of the iso-2593 34 pin connec- tor. (see figure 46 connector drawings on page 73). the XRT4500 contains a sufficient number of receiv- ers, transmitters and transceivers to transport all of the signals required for each of the above-mentioned communication interface standards. by configuring the XRT4500 to operate in a particular communica- tion interface mode, each of the transmitters and receivers will automatically be configured to support the appropriate electrical interface requirements. table 3 and table 4 present the relationship between the communication interface mode that the XRT4500 has been configured to operate in and the corresponding electrical interface mode that a giv- en transmitter or receiver will be automatically con- figured in. table 3 presents this information for the XRT4500 configured to operate in the dte mode. table 4 pre- sents this information when the XRT4500 has been configured to operate in the dce mode.
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 38 t able 3: dte m ode - c ontrol p rogramming for d river and r eceiver m ode s election i nterface s tandard c ontrol i nputs m2 m1 m0 driver/receiver pair and corresponding signal name - dte mode tx1 rx1 txd rxd tx2 rx2 scte rxc tx3 rx3 - txc tx4 rx4 rts cts tx5 rx5 dtr dsr tx6 rx6 - dcd tx7 rx7 ll - tx8 rx8 rl ri/tm v.10 0 0 0 v.10 v.10 v.10 v.10 off v.10 v.10 v.10 v.10 v.10 off v.10 v.10 off v.10 v.10 eia-530-a (v.11) 0 0 1 v.11 v.11 v.11 v.11 off v.11 v.11 v.11 v.10 v.10 off v.11 v.10 off v.10 v.10 eia-530, rs449, v. 3 6 0 1 0 v.11 v.11 v.11 v.11 off v.11 v.11 v.11 v.11 v.11 off v.11 v.10 off v.10 v.10 x.21 0 1 1 v.11 v.11 v.11 v.11 off v.11 v.11 v.11 v.11 v.11 off off off off off off v.35 1 0 0 v.35 v.35 v.35 v.35 off v.35 v.28 v.28 v.28 v.28 off v.28 v.28 off v.28 v.28 reserved 1 0 1 v.11 v.11 v.11 v.11 off v.11 v.11 v.11 v.11 v.11 off v.11 v.10 off v.10 v.10 rs232 (v.28) 1 1 0 v.28 v.28 v.28 v.28 off v.28 v.28 v.28 v.28 v.28 off v.28 v.28 off v.28 v.28 power down 1 1 1 off off off off off off off off off off off off off off off off t able 4: dce m ode - c ontrol p rogramming for d river and r eceiver m ode s election i nterface s tandard c ontrol i nputs m2 m1 m0 driver/receiver pair and corresponding signal name - dce mode tx1 rx1 rxd txd tx2 rx2 rxc scte tx3 rx3 txc - tx4 rx4 cts rts tx5 rx5 dsr dtr tx6 rx6 dcd - tx7 rx7 - ll tx8 rx8 ri/tm rl v.10 0 0 0 v.10 v.10 v.10 v.10 v.10 off v.10 v.10 v.10 v.10 v.10 off off v.10 v.10 v.10 eia-530-a (v.11) 0 0 1 v.11 v.11 v.11 v.11 v.11 off v.11 v.11 v.10 v.10 v.11 off off v.10 v.10 v.10 eia-530, rs449, v. 3 6 0 1 0 v.11 v.11 v.11 v.11 v.11 off v.11 v.11 v.11 v.11 v.11 off off v.10 v.10 v.10 x.21 0 1 1 v.11 v.11 v.11 v.11 v.11 off v.11 v.11 v.11 v.11 off off off off off off v.35 1 0 0 v.35 v.35 v.35 v.35 v.35 off v.28 v.28 v.28 v.28 v.28 off off v.28 v.28 v.28 reserved 1 0 1 v.11 v.11 v.11 v.11 v.11 off v.11 v.11 v.11 v.11 v.11 off off v.10 v.10 v.10 rs232 1 1 0 v.28 v.28 v.28 v.28 v.28 off v.28 v.28 v.28 v.28 v.28 off off v.28 v.28 v.28 power down 1 1 1 off off off off off off off off off off off off off off off off
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 39 1.2 the system architecture the XRT4500 contains the following functional blocks. ? the high-speed transceiver block ? the handshaking/control transceiver block ? the diagnostic operation indicator transceiver block ? the control block block diagrams are located on page 1 and 2. the figures illustrate how the eight receivers and transmitters in the XRT4500 are grouped into the high-speed transceiver block, the handshaking/control trans- ceiver block and the diagnostic operation indicator transceiver block. the control block permits the user to implement the following configuration options in the XRT4500. ? select which communication interface mode the XRT4500 will operate in. (rs-252, v.36, etc.) ? configure the XRT4500 into either the dte or the dce mode. ? configure the XRT4500 to operate in a loop-back mode. ? enable the echo-clock mode. ? configure the XRT4500 into the latch mode. ? configure the XRT4500 into the register mode. ? configure the XRT4500 into either the 2-clock or the 3-clock mode. ? enable the internal oscillator, in order to support stand-alone dte diagnostic operation. ? invert the txc clock signal (for dce application) or the rxc clock signal (for dte applications). ? invert the txd signal (for dte applications) or the rxd signal (for dce applications). ? enable the x.21 mode. a more detailed discussion of the control block can be found in section 1.2.4. figure 12, figure 13, figure 14, and figure 15 are a set of functional block diagrams that give more de- tailed information about the four functional blocks shown in the top-level diagram. figure 12 presents detailed information on the high-speed transceiver block. figure 13 presents detailed information about the handshaking/control transceiver block. figure 14 presents detailed information about the di- agnostic operation indicator transceiver block. fi- nally, figure 15 presents some detailed information about the control block.
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 40 1.2.1 the high -speed transceiver block the high-speed transceiver block supports the transmission and reception of high speed data and clock signals for the selected communication inter- face. this block contains receivers rx1 and rx2, transmitters tx1 and tx2, and bi-directional trans- ceiver tr3 which is composed of tx3 and rx3. each of these devices may be configured to support the electrical interface requirements per itu-t v.35, itu-t v.11 (eia-422), itu-t v.10 (eia-423), or itu-t v.28 (eia-232). in the itu-t v.35 mode, each trans- mitter has a common mode pin that is connected to the center of the internal termination. this pin should be bypassed to ground with an external 0.1f capac- itor in order to provide the best possible driver output stage balance. in a system application, the tx1-rx1 pair and tx2-rx2 pair handle the txd-rxd (transmit data - receive data) and the txc-rxc (transmit clock - receive clock) high speed interface signals respectively. trans- ceiver tr3 is dedicated to the scte (transmit clock echo) signal for both dce and dte modes of operation. transceiver tr3 functions as a receiver for the dte mode and as a transmitter during the dce mode. f igure 12. h igh -s peed t ransceiver b lock
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 41 1.2.2 the handshaking/control signal trans- ceiver block the handshaking/control signal transceiver block contains receivers rx4 and rx5, transmitters tx4 and tx5, and a transceiver tr6 which is composed of tx6 and rx6. each of these devices may be con- figured to support the electrical interface require- ments per itu-t v.11 (eia-422), itu-t v.10 (eia- 423), or itu-t v.28 (eia-232). the rx4-tx4 pair is dedicated for the rts (request to send) and cts (clear-to-send) signals while rx5-tx5 are intended to support the dtr (data terminal ready) and the dsr (data set ready) signals. transceiver tr6 supports the dcd (data carrier detect) signal. f igure 13. h andshaking /c ontrol t ransceiver b lock
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 42 1.2.3 the diagnostic operation indicator transceiver block the diagnostic operation indicator transceiver block contains transceiver tr7, which is composed of tx7 and rx7, receiver rx8 and transmitter tx8. these devices may be configured to support the electrical interface requirements, per itu-t v.10 (eia-423) or itu-t v.28 (eia-232). these devices were specifically designed to support the local lock (ll), remote loopback (rl) and ri (or tm) signals. f igure 14. d iagnostic o peration indicator t ransceiver b lock
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 43 1.3 t he c ontrol b lock the purpose of the control block is to permit the user to configure the XRT4500 into a wide variety of oper- ating modes. in particular, the control block permits the user to implement the following configuration se- lections for the XRT4500. to select which communication interface mode the XRT4500 will operate in. ? to configure the XRT4500 to operate in either the dte or the dce mode. ? to optionally configure the XRT4500 to operate in a loop-back mode. ? to enable or disable the echo-clock mode. ? to optionally configure the XRT4500 to operate in the latch mode. ? to optionally configure the XRT4500 to operate in the register mode. ? to configure the XRT4500 to operate in either the 2 clock or the 3-clock mode. ? to enable or disable the internal oscillator (for dte stand-alone diagnostic operation). ? to invert the txc clock signal (for dce applica- tions) or the rxc clock signal (for dte applica- tions). ? to invert the txd data (for dce applications) or the rxd data (for dte applications). the input pins shown in figure 15, the control block, are described in detail, below. f igure 15. d iagram of the XRT4500 c ontrol b lock
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 44 1.3.1 m[2:0] - the (communication interface) mode control select pins. as mentioned earlier, the XRT4500 is capable of sup- porting each of the following communication inter- face standards. ? itu-t v.35 ? itu-t v.28 (eia-232) ? eia-449 ? itu-t v.36 ? itu-t x.21 ? eia-530 ? eia-530(a) the XRT4500 can be configured to operate in either one of these communication interface standards, by setting the m[2:0] bit-fields to the appropriate val- ues, as listed in table 5. n ote : the m[2:0] input pins are internally pulled high. as a consequence, the XRT4500 will automatically be config- ured into the power-down mode, if the m[2:0] input pins are left floating. t able 5: t he r elationship between the settings for the m[2:0] bit - fields and the c orresponding c ommunication i nterface that is supported c ommunication i nterface m2 m1 m0 c omments rs423 (v.10) 0 0 0 all transmitters and receivers are functioning in the v.10 mode. n ote : this is not a standard communication interface. eia-530a (v.11) 0 0 1 eia-530 (v.36) 0 1 0 rs449 010 x.21 011 v.35 100 reserved 101 rs232 (v.28) 1 1 0 power down mode 1 1 1 all transmitters and receivers are shut-off. transmitter outputs are tri-stated and all internal loads are disconnected. the charge pump and dc-dc con- nect continues to operate.
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 45 1.3.2 dce/ dte - the dce/ dte mode select pin the XRT4500 is capable of supporting either the "dce" or "dte" modes of operation. setting this in- put pin "high" configures the XRT4500 to operate in the "dce" mode. conversely, setting this input pin "low" configures the XRT4500 to operate in the "dte" mode. a brief description of dce mode and dte mode operations are listed below. figure 16 presents a very simple illustration of a dce terminal being interfaced to a dte terminal. from this figure, one can make the following observations about the dce and dte terminals. the dce terminal the dce terminal is responsible for sourcing/gener- ating all of the following signals. ? rxd - receive data (high speed signal) ? rxc - receive clock (high speed signal) ? txc - transmit clock (high speed signal) ? dsr - data set ready ? dcd - data carrier detect ? cts - clear to send ? ri (ring indicator) or ? tm (test mode). further, the dce terminal is responsible for receiving/ terminating all of the following signals. ? txd - transmit data (high speed signal) ? txce (or scte) - transmit clock echo (high speed signal) ? dtr - data terminal ready ? rts - request to send ? ll - local loop-back indicator ? rl - remote loop-back indicator because of this, whenever the XRT4500 is configured to operate in the dce mode, then the following con- figuration conditions are true. ? three high-speed transmitters are enabled, and ? two high-speed receivers are enabled. ? four low-speed transmitters are enabled, and ? four low-speed receivers are enabled. f igure 16. a s imple i llustration of the dce/dte i nterface txd txc rxd rxc txce dtr dsr dcd cts rts ll rl ri (or tm) dte equipment dce equipment XRT4500 XRT4500
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 46 the dte terminal the dte terminal is responsible for sourcing/gener- ating all of the following signals. ? txd - transmit data ? txce (or scte) - transmit clock echo ? dtr - data terminal ready ? rts - request to send ? ll - local loop-back indicator ? rl - remote loop-back indicator further, the dte terminal is responsible for receiv- ing/terminating all of the following signals. ? rxd - receive data ? txc - transmit clock ? rxc - receive clock ? dsr - data set ready ? dcd - data carrier detect ? cts - clear-to-send ? ri (ring indicator) ? tm (test mode indicator). because of this, whenever the XRT4500 is configured to operate in the dte mode, then the following con- figuration conditions are true. ? two high-speed transmitters are enabled, and ? three high-speed receivers are enabled. ? four low-speed transmitters are enabled, and ? four low-speed receivers are enabled. other comments about dce and dte equipment whenever dce and dte equipment are interfaced to each other, the dce equipment is typically the source of all timing signals. the dte equipment will typically function as a clock slave. 1.3.3 the lp - loop-back enable/disable select pin as mentioned earlier, the XRT4500 can be configured to operate in the loop-back mode. setting the lp in- put pin high disables the loop-back mode (within the XRT4500). conversely, setting this input low config- ures the XRT4500 to operate in the txd/rxd loop- back mode. a detailed description of the txd/rxd loop-back mode is presented below. behavior of dte/dce mode devices, when the loop-back mode is disabled figure 17 presents an illustration of a dte and dce terminal interfaced to each other when no XRT4500 loop-back mode has een configured. f igure 17. i llustration of both the dte and dce m ode XRT4500 operating , when the l oop -b ack m ode is disabled dte (#2) scc (l) XRT4500 XRT4500 rx1 tx1 rx2 tx2 rx3 tx3 rx2 tx2 rx1 tx1 rxd rxc txc scte_in txd_in txd scte txc_in rxc_in rxd_in 60 67 73 74 1 78 79 77 76 70 71 64 65 63 62 1 74 68 67 60 63 62 64 65 70 71 77 76 78 79 txd txc rxc rxd scc (r) dte (#1)* scte * indicates scenario # from table 8
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 47 figure 27 indicates that the dte serial communica- tions controller (scc) sources the txd signal. this digital signal is then converted into an analog line signal (as dictated by the m[2:0] settings) by the dte mode XRT4500. this line signal is then trans- mitted over the dte/dce interface and is received by the dce terminal. this analog line signal is then converted back into the digital format by the dce mode XRT4500. this digital signal is ultimately re- ceived and terminated by the dce scc (serial com- munications controller). likewise, this figure indicates that the rxd signal is sourced by the dce scc. this digital signal is then converted into an analog line signal by the dce mode XRT4500. this line signal is then transported over the dce/dte interface and is re- ceived by the dte mode XRT4500. this analog line signal is then converted back into the digital format by the dte mode XRT4500. the XRT4500 then outputs this signal to the dte scc. this is considered to the be the normal (non-loop-back/diagnostic) mode of operation. n ote : figure 27 only depicts the high-speed dce/dte interface signals. the low-speed control/handshaking signals are not affected by the loop-back mode. behavior of the dte mode XRT4500, when the loop-back mode is enabled. figure 18 presents an illustration of a dte and a dce terminal interfaced to each other. in this case, the XRT4500 (associated with the dte terminal) has been configured to operate in the loop-back mode n ote : figure 18 only depicts the high-speed signals. the low-speed control/handshaking signals are not affected by the loop-back mode. if the loop-back mode is configured within the XRT4500, while it is operating in the dte mode, then the following two (2) loop-back paths will exist. ? a digital/terminal-side loop-back ? an analog/line-side loop-back each of these loop-back paths are described below. 1. the digital/terminal side loop-back path: this loop-back path is referred to as a digital/termi- nal side loop-back, because all signals originate from and are terminated by the dte scc (e.g., the terminal equipment). the signals (from the dte scc) are never converted into the analog format, and are not outputted to the line. the txd signal (originating from the dte scc), along with the scte (transmit echo clock) will be not be outputted to the dce terminal. instead, this signal will be loop-back into the dte scc. the txd sig- nal will ultimately be outputted to the dte scc via the rxd output pin of the dte mode XRT4500. the scte signal will ultimately output the dte scc via the rxc output pin of the XRT4500. n ote : since the dte scc requires the txc signal (in order to synthesize the scte signal), this loop-back still permits the txc signal to pass through to the dte scc. f igure 18. i llustration of the b ehavior the dte m ode XRT4500, when it is configured to operate in the l oop -b ack m ode scc (r) scc (l) XRT4500 XRT4500 rx1 tx1 rx2 tx2 rx3 tx3 rx2 tx2 rx1 tx1 rxd rxc txc scte_in txd_in txd scte txc_in rxc_in rxd_in 60 67 73 74 1 78 79 71 77 70 71 64 65 63 62 1 74 68 67 60 63 62 64 65 70 71 77 76 78 79 txd scte txc rxc rxd digital/terminal loop-back path analog/line loop-back path mux 1 dce (#2) dte (#3)
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 48 2. the analog/line-side loop-back path: this loop-back path is referred to as an analog/line- side loop-back, because all signals originate from and are ultimately terminated by the dce terminal. these signals originate from the dce terminal; and are out- putted to the line, to the dte terminal. however, these signals (from the dce terminal) are never converted in- to the digital format (by the dte mode XRT4500). these signal are kept in the analog format, and are looped-back (over the line) to the dce terminal. the rxd signal (originating from the dce terminal) will be transmitted over the line to the dte terminal. however, this signal will not be converted into the dig- ital format by the dte mode XRT4500. instead, this signal will be looped-back out to the dce terminal via the txd signal path. n ote : in this loop-back mode, the rxc signal (e.g., the companion clock signal to rxd) is also received by the dte terminal and looped-back out to the dce terminal. in this case, the rxc (receive clock) signal will be routed to the dce terminal through the scte signal path the dce scc can still use the rxc (via the scte signal path), in order to sample the rxd signal (which is available via the txd signal path). behavior of the dce mode XRT4500, when the loop-back mode is enabled. figure 19 presents an illustration of a dte and a dce terminal interfaced to each other. in this case, the XRT4500 (associated with the dce terminal) has been configured to operate in the loop-back mode. n ote : figure 19 only depicts the high-speed dce/dte interface signals. the low-speed control/handshaking signals are not affected by the loop-back mode. if the loop-back mode is configured within the XRT4500, while it is operating in the dce mode, then the following two (2) loop-back paths exists. ? a digital/terminal-side loop-back ? an analog/line-side loop-back each of these loop-back paths are described below. 1. the digital/terminal side loop-back: again, this loop-back path is referred to as a digital/ terminal side loop-back, because all of the signals originate from, and are terminated by the dce scc (e.g., the terminal equipment). the signals (originat- ing at the dce scc) are not converted into the ana- log format, and are not output to the line. the rxd signal (originating from the dce scc) along with the rxc (receive clock) signal will not be converted into the analog format, nor output to the dte terminal (over the line). instead, this signal will remain in the digital-format and will be looped-back into the dce scc. the rxd signal will ultimately be output to the dce scc via the txd output of the dce mode XRT4500. n ote : the rxc signal (e.g., the companion clock signal to rxd) will also be loop-back into the dce scc. this signal will be output (by the XRT4500) via the scte output pin. f igure 19. i llustration of the b ehavior of the dce m ode XRT4500, when it is configured to operate in the l oop - back m ode scc (r) scc (l) XRT4500 XRT4500 rx1 tx1 rx2 tx2 rx3 tx3 rx2 tx2 rx1 tx1 rxd rxc txc scte_in txd_in txd scte txc_in rxc_in rxd_in 60 67 73 74 1 78 79 77 76 70 71 64 65 63 62 1 74 68 67 60 63 62 64 65 70 71 77 76 78 79 txd scte txc rxc rxd analog/line loop-back path digital/terminal loop-back path dte (#1) dce (#4) mux 1
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 49 2. the analog/line-side loop-back: this loop-back path is referred to as an analog/line- side loop-back, because all signals originate from and are terminated by the dte terminal (over the line). these signals originate from the dte terminal, and are output, over the line, to the dte terminal. however, these signal (originating from the dte ter- minal) are never converted into the digital format (by the dce mode XRT4500). these signals are kept in the analog format, and are looped-back (over the line) to the dte terminal. the txd signal (originating from the dte terminal) will be transmitted over the line to the dce terminal. however, this signal will not be converted into the dig- ital format by the dce mode XRT4500. instead, this signal will be loop-back to the dte terminal, via the rxd signal path. n ote : in this loop-back mode, the scte signal (e.g., the companion clock signal to txd) is also received by the dce terminal and is looped-back to the dte terminal. in this case, the scte signal will be routed through the rxc path. the dte scc can use this signal to sample the txd (now rxd signal). 1.3.4 the ec* (echo clock mode - enable/ disable select input pin) a wide variety of serial communications controller (sccs) are deployed in either dte or dce type of data communications equipment. these sccs can be realized in an asic solution or they can be a stan- dard product. an example of a standard product scc, would be the am85c30 from amd. one variation that exists among these sccs are in the number of clock signals that these chips use and process, in order to support data communica- tions over a dte/dce interface. for example, some sccs process 3 clock signals in order to support the transmission/reception of data over a dte/dce inter- face. other sccs process only 2 or 1 clock signals. examples of a 3-clock and a 2-clock dte/dce interface are presented below. the 3-clock dce/dte interface many of the data communication standards (e.g., itu-t v.35, eia-530(a), etc.) define three clock sig- nals that are to be transported over the dte/dce in- terface. these tree clock signals are listed below. ? txc - transmit clock ? rxc - receive clock ? scte (or txce) - transmit clock echo figure 20 presents an illustration of a dte and dce exchanging data over a 3-clock dte/dce interface. f igure 20. i llustration of a typical 3-c lock dce/dte i nterface scc (r) scc (l) XRT4500 XRT4500 rxd rxc txc scte_in txd_in txd scte txc_in rxc_in rxd_in 60 67 73 2 74 1 78 79 77 76 70 71 64 65 63 62 1 74 68 67 60 63 62 64 65 70 71 77 76 78 79 txd scte txc rxc rxd dte (#1) dce (#2) tx1 rx1 rx2 tx3 tx2 tx1 rx2 rx3 tx2 rx1
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 50 the important things to note about figure 20 are as follows. 1. the dce terminal is the ultimate source of all clock signals. 2. the dce serial communications controller (scc) will transmit the txc clock signal to the dte node. 3. the dte scc will update the state on the txd line, upon the rising edge of the incoming txc clock signal when clock invert is not activated. 4. the dte scc will generate the rising edge of the scte clock signal, upon receipt of the rising edge of the incoming txc clock signal when clock invert is not activated. 5. the dce scc will use the falling edge of the scte clock signal in order to sample the incoming txd signal. 6. because the dte provides the scte clock signals and since the falling edge of this clock signal will oc- cur at the middle of the bit-period (for the signal on the txd line); the 3-clock dte/dce interface is largely immune to the affects of propagation delay (via the dce scc to dte scc link and the dte scc to dce scc link), and will operate properly over a very wide range of data rates. figure 21 presents an illustration of the wave-forms of the signals that are transported across a 3-clock dte/dce interface. further, this figure indicates that a 3-clock dte/dce interface provides the dce scc with a txd to txc set-up time of one-half of the bit-period (0.5 * tb). hence, a 3-clock dte/dce interface can support very wide range of data rates, and still insure that the dce scc will be provided a sufficient txd to txc set-up time. the 2-clock dte/dce interface although the data communications standards rec- ommends the use of these three clock signals; in practice, some data communications equipment manufacturers will build equipment that only supports the transmission of 2-clock signals. the reason for this can be due to cost, or due to the fact that the da- ta communications equipment manufacturer is using an scc that only handles 2-clock signals. when data communications equipment manufacturers design their dce or dte equipment to only support the transmission of two clocks over the dte/dce inter- face; these two clocks signals are typically the txc (transmit clock) and the rxc (receive clock) sig- nals. figure 22 presents an illustration of a dte and dce exchanging data over a 2-clock dce/dte in- terface. n ote : in the 2-clock dte/dce interface, the dte termi- nal does not supply the scte clock signal back to the dce. f igure 21. i llustration of the wave - forms of the signals that are transported across a 3-c lock dte/dce i nterface txc (at dce) txc (at dte) txd (at dte) txd (at dce) 0.5*tb scte (at dte) scte (at dce)
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 51 since the dte scc will not provide the dce scc with the scte signal, the dce scc will have to use a different clock signal in order to sample the incom- ing data on the txd line. a common approach, in this case, is to simply hard-wire the txc output signal to the scte input pin of the dce scc) and to use the falling edge of the txc clock signal in order to sample the incoming data on the txd line, as il- lustrated above in figure 1.8. n ote : there are numerous bad things about designing dce equipment, per the illustration in figure 1.9. in addi- tion to the reasons presented below, since the dce scc is now hard-wired to use the txc as the means to sample the incoming txd signal, this approach is not flexible if the user is interfacing to a dte that happens to support 3- clock signal. in this case, the user is advised to consider using the 2-clock mode feature (which is also offered by the XRT4500) and is discussed in section 1.2.5. important things to note about figure 1.9. 1. the dte scc will not supply the scte signal to the dce scc. 2. the dce scc will use the falling edge of the (lo- cally generated) txc clock signal in order to sample the incoming txd signal. unlike the 3-clock dte/dce interface, the 2-clock dte/dce interface is sensitive to the round-trip propagation delay between the dce and the dte terminals (due to the cable, components comprising the dce and dte terminals, etc.) an example of this sensitivity is presented below. case 1 - 2-clock dte/dce operation at 1.0mbps consider the case where the dce and dte are ex- changing data at a rate of 1.0mbps. further, let's con- sider that the total propagation delay from the dce to the dte is 160 ns. likewise, let's consider that the to- tal propagation delay from the dte to the dce is also 160ns. given these conditions, figure 23 plots out the clock and signal wave-forms for the txc and txd at both the dce and dte sccs. f igure 22. i llustration of a 2-c lock dte/dce i nterface 2 scc (r) scc (l) XRT4500 XRT4500 rx1 tx2 rxd rxc txc scte_in txd_in txd scte txc_in rxc_in rxd_in 60 67 73 74 1 78 79 77 76 70 71 64 65 63 62 1 74 68 67 60 63 62 64 65 70 71 77 76 78 79 txd txc rxc rxd dce dte tx1 rx3 rx2 rx1 rx2 tx3 tx2 tx1
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 52 figure 23 indicates that the txc (transmit clock) sig- nal will originate at the dce scc terminal. however, because of the dce-to-dte propagation delay, the txc signal will arrive at the dte scc 160ns later. per the various communication interface standards (e.g., eia-530a, etc.), the dte must update the data on the txd line upon detection of the rising edge of the incoming txc clock signal. hence, figure 1.10 illustrates the dte scc toggling the txd line coinci- dent with the rising edge of txc. finally, because of the dte to dce propagation delay, the txd signal will arrive at the dce scc 160 ns later. recall that the dce scc is using the txc clock sig- nal to sample the data on the incoming txd line. the scenario depicted in figure 1.10 indicates that if the data rate (between the dce and dte) is 1.0mbps; and that if the dce to dte and dte to dce propagation delays are each 160ns, then the dce scc will be provided with 180ns of set-up time, (in the txd line) prior to sampling the data. for most digital ics, this amount of set-up time is sufficient long and should not result in any bit errors. case 2 - 2 clock dce/dte operation at 1.544 mbps now let's consider the case where the dce and dte terminals are now exchanging data at a rate of 1.544mbps (e.g., the ds1 rate). further, let's consid- er that the dce-to-dte and dte-to-dce propa- gation delays are each 160ns (as in the prior case). given these conditions, figure 24 illustrates the re- sulting clock and signal wave-forms for the txc and txd at both the dce and dte sccs. the scenario depicted in figure 24 indicates that if the data rate (between the dce and the dte) is 1.544mbps and that if the dce-to-dte and the dte-to-dce propagation delays are each 160ns, then the dce scc will be provided with 4ns of set-up time (in the txd line) prior to sample the data. for f igure 23. t he b ehavior of the txc and txd s ignals at the dce and dte scc s , (d ata r ate = 1.0m bps , dce- to -dte propagation delay = 160 ns , dte- to -dce propagation delay = 160 ns ) txc (at dce) txd (at dte) txc (at dte) txd (at dce) 1us 500ns 180ns f igure 24. t he b ehavior of the txc and txd s ignals at the dce and dte scc s (d ata r ate = 1.544m bps , dce- to -dte p ropagation d elay = 160 ns , dte- to -dce p ropagation d elay = 160 ns ) txc (at dce) txd (at dte) txc (at dte) txd (at dce) 648ns 324 ns 4ns
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 53 some digital is, this amount of set-up time is marginal and is likely to result in bit-errors. throughout the re- mainder of this document, this phenomenon will be referred to as the 2-clock/propagation delay phe- nomenon. cases 1 and 2 indicate that if a wide range of data rates are to be supported by some data communica- tion equipment over a 2-clock dte/dce interface' and if the propagation delays are sufficiently large (in the dce-to-dte and dte-to-dce link); then there are some data rates that will be handled in an error- free manner; and other data rates which are prone to errors. consequently, the 3-clock dte/dce inter- face is a much more robust and reliable medium to transport data, than is the 2-clock dte/dce inter- face. using the echo-clock feature within the XRT4500 the echo-clock features within the XRT4500 helps to mitigate the 2-clock/propagation delay phenom- enon by forcing the dte mode XRT4500 to supply an additional clock signal (over the dte/dce interface), over and above that provided by the dte scc. figure 25 presents an illustration of the echo clock feature (within the dte mode XRT4500) being used. in the example, presented in figure 25, the dte scc does not supply the scte signal to the dte/dce in- terface (just as in the two previous examples). how- ever, in this case, the XRT4500 (on the dte side) has been configured to operate in the echo-clock mode. while the XRT4500 is operating in this mode, it will simply take the incoming transmit clock signal (txc) and will echo it back to the scte input pin of the dce scc. if we were to closely analyzer the clock signals that are transported across the dte/ dce interface, in order to determine the resulting txc to txd set-up time, we would observe the fol- lowing. 1. the dce scc sources the txc clock signal to the dte node. 2. the dte scc will update the state of the txd line on the rising edge of the incoming txc clock signal. 3. the dte XRT4500 will internally route the rx3d output signal to the tx2d output signal. as a consequence, the incoming txc clock signal will be echoed back out to the scte input pin of the dce scc. 4. if we neglect the clock-to-output delay of the dte scc, the dce scc will receive the falling edge of the scte clock signal, very close to the middle of the bit-period of each bit on the txd line. this phenomenon is also illustrated below in figure 26. f igure 25. i llustration of the e cho -c lock f eature within the XRT4500 scc (r) scc (l) XRT4500 XRT4500 rx1 tx2 rxd rxc txc scte_in txd_in txd scte txc_in rxc_in rxd_in 60 67 73 74 1 78 79 77 76 70 71 64 65 63 62 1 74 68 67 60 63 62 64 65 70 71 77 76 78 79 txd scte txc rxc rxd dce dte tx1 rx3 rx2 rx1 rx2 tx3 tx2 tx1
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 54 by using the echo-clock feature, within the XRT4500, the overall system (comprised of the dte and dce terminals) is nearly as immune to the 2-clock/propagation delay phenomenon, as is the 3-clock dte/dce interface; even though the dte scc only processes two clock signals. hence, in short, the purpose of the echo-clock mode is to provide the overall-system with the scte clock signal, when it is not being supplied by the dte scc. the impact of being able to accomplish this is a more robust, reliable system performance. configuring the echo-clock mode the user can configure the echo-clock mode, with- in the XRT4500, by pulling the ec input pin (pin 34) low. conversely, the user can disable the echo- clock mode by pulling the ec input pin high. when the ec input pin is pulled low, then the XRT4500 will internally use the txc digital signal (which is output, from the dte mode XRT4500, via the rx3d output pin) as the source for the scte (or the tx2d) signal. n ote : the echo-clock mode is only available if the XRT4500 is operating the dte mode. 1.3.5 the 2ck/3ck (2-clock/3-clock mode - enable/disable select input pin) section 1.3.4 discusses the echo-clock mode, and how it can be used to combat the 2-clock/propaga- tion delay phenomenon. the echo-clock mode is an approach that can be used to attack this phenom- enon, if the XRT4500 is designed into a dte equip- ment. however, if a system manufacturer, of dce equipment, encounters this problem, one is not able to configure a way out of this phenomenon by en- abling the echo-clock mode. fortunately, the XRT4500 does offer the dce equipment design a couple of another options which can be used to miti- gate the 2-clock/propagation delay phenomenon. these two features are: ? the 2-clock/3-clock mode feature ? the clock inversion feature this section discusses the 2-clock/3-clock feature. as mentioned above, if the dte/dce interface only consists of two clock signals, (e.g., missing the scte signal), then there will be some data rates at which the dce scc will not be provided with sufficient set- up time, when sampling the txd signal. figure 27 presents an illustration of two XRT4500 be- ing implemented in a dte/dce interface. in this fig- ure, the dce mode XRT4500 has been configured to operate in the 2-clock mode. when the XRT4500 is configured to operate in the 2-clock mode, then it will internally use the txc signal as a means to syn- thesize the scte clock signal (as depicted below). f igure 26. i llustration of the w ave - forms , across a dce/dte i nterface , when the e cho -c lock f eature ( within the XRT4500) is used as depicted in f igure 25 txc (at dce) txc (at dte) txd (at dte) txd (at dce) 0.5*tb scte (at dte) scte (at dce)
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 55 in this case, the 2-clock mode offers a considerable amount of design flexibility. this approach permits the dce equipment system design engineer to design and layout a board that can be automatically config- ured to support either the 3-clock mode (if all three clock signals are present, over the dte/dce inter- face). further, this approach also permits the system design engineer to configure the XRT4500 into the 2-clock mode (if the scte clock signal is not present). this feature is a nice alternative to hard- wiring the txc output (of the dce scc) to the scte input. n ote : the 2-clock mode feature, by itself, does not solve the 2-clock/propagation delay phenomenon. however, the 2-clock mode, within the XRT4500, permits the user to do the following. a. to configure the XRT4500 to automatically operate in the 3-clock mode, whenever it is interfaced to a dte that supports all three (3) clock signals, or b. to configure the XRT4500 to automatically operate in the 2-clock mode, whenever it is interfaced to a dte that only supports two (2) clock signals. once the user has configured the XRT4500 to operate in the 2-clock mode, then the user can solve the 2- clock/propagation delay phenomenon by invoking the clock inversion feature, as described below in section 1.2.6. configuring the 2-clock mode. the user can configure the XRT4500 to operate in the 2-clock mode by setting the 2ck/3ck input pin high. conversely, the user can disable the 2- clock mode (otherwise known as operating the XRT4500 in the 3-clock mode) by setting the 2ck/ 3ck input pin low. 1.3.6 the clock inversion (ck_inv) feature the XRT4500 can be configured to invert the txc signal by setting the ck_in input pin (pin 54) low. setting the ck_inv input to high removes the in- vert from the txc signal path. an illustration of the dce mode XRT4500, configured to invert the txc signal is illustrated in figure 28. f igure 27. i llustration of the dce/dte i nterface , with the dce m ode XRT4500 operating in the 2- c lock m ode dce scc (l) XRT4500 XRT4500 rx1 tx1 rx2 tx2 rx3 tx3 rx2 tx2 rx1 tx1 rxd rxc txc scte_in txd_in txd scte txc_in rxc_in rxd_in 60 67 73 74 1 78 79 77 76 70 71 64 65 63 62 1 74 68 67 60 63 62 64 65 70 71 77 76 78 79 txd txc rxc rxd scc (r) dte
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 56 the clock inversion feature is also available if the XRT4500 is operating in the dte mode. figure 29 presents an illustration of a dte mode XRT4500, when it is configured to invert the txc clock signal. the benefits of the clock inversion feature in section 1.3.4 of this document, a lengthy discussion, regarding the 2-clock/propagation delay phenomenon is presented. in this section, the echo-clock fea- ture was also presented as a possible solution to the 2-clock/propagation delay phenomenon. however, the echo-clock feature has a drawback. if a dce equipment manufacturer were to interface his/her equipment to a dte terminal that does not support f igure 28. i llustration of the dce m ode XRT4500 being configured to invert the txc signal scc (r) scc (l) XRT4500 XRT4500 rx1 tx1 rx2 tx2 rx3 tx3 rx2 tx2 rx1 tx1 rxd_out rxc txc scte_in txd_in txd scte txc_in rxc_in rxd_in 60 67 73 74 1 78 79 77 76 70 71 64 65 63 62 1 74 68 67 60 63 62 64 65 70 71 77 76 78 79 txd scte txc rxc rxd dce dte f igure 29. i llustration of the dte m ode XRT4500 being configured to invert the txc signal scc (r) scc (l) XRT4500 XRT4500 rx1 tx1 rx2 tx2 rx3 tx3 rx2 tx2 rx1 tx1 rxd rxc txc scte_in txd_in txd scte txc_in rxc_in rxd_in 60 67 73 74 1 78 79 77 76 70 71 64 65 63 62 1 74 68 67 60 63 62 64 65 70 71 77 76 78 79 txd scte txc rxc rxd dce dte
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 57 the scte clock signal; it is highly unlikely that the dce equipment manufacturer will be able to (over the dte/dce interface) invoke the echo-clock mode and resolve the 2-clock/propagation delay phenomenon. n ote : this is especially the case if the dte equipment is not using the XRT4500 as the multi-protocol transceiver ic. as a consequence, the dce equipment manufac- turer would have to resort to undesirable things, such as using the (locally generated) txc signal as the sampling clock for the txd signal. however, the XRT4500 does offer the dce equip- ment manufacturer an elegant solution to the 2- clock/propagation delay phenomenon. by doing the following things. a. configuring the dce mode XRT4500 to operate in the 2-clock mode, and b. inverting the txc signal, within the dce mode XRT4500, the user can largely resolve the 2-clock/ propagation delay phenomenon. figure 30 presents an illustration of the dce mode XRT4500, being configured to (1) operate in the 2- clock mode, and (2) to invert the txc signal. by taking advantage of both the 2-clock mode and the ability to invert the txc clock signal, the dce equipment manufacture can mitigate the 2-clock/ propagation delay phenomenon by simply inverting the txc whenever the dte/dce interface and sys- tem configuration settings begin to violate the txd to txc set-up time requirement of the dce scc de- vice. by inverting the txc signal, the phase relation- ship, between the txd and the txc signal will shift by 180 degrees. at this point, the sampling edge of the txc signal will be near the middle of the txd bit-period, and the system will not be violating the txd to txc set-up time requirements of the dce scc device. in summary, the 2-clock mode (within the XRT4500) provides the user with the following op- tions. the dce equipment (which uses the XRT4500) can easily be configured to interface to dte equipment that supports the scte clock signal, as well as dte equipment that does not support the scte clock sig- nal. if the dce equipment is being interfaced to a dte which supports the scte clock signal, then the dce equipment should configure the XRT4500 to op- erate in the 3-clock mode. conversely, if the dce equipment is being interfaced to a dte which does not support the scte clock signal, then the dce equipment should configure the XRT4500 to operate in the 2-clock mode. this step will automatically configure the XRT4500 to route the txc clock sig- f igure 30. i llustration of the dce m ode XRT4500, which is operating in the 2-c lock m ode , and inverting the txc signal scc (r) scc (l) XRT4500 XRT4500 rx1 tx1 rx2 tx2 rx3 tx3 rx2 tx2 rx1 tx1 rxd_out rxc txc scte_in txd_in txd scte txc_in rxc_in rxd_in 60 67 73 74 1 78 79 77 76 70 71 64 65 63 62 1 74 68 67 60 63 62 64 65 70 71 77 76 78 79 txd scte txc rxc rxd dce dte
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 58 nal to the scte_in input pin of the dce scc. there is no need to design in extra glue logic to multi- plex the scte output pin of the XRT4500 with the txc output pin of the dce scc. additionally, if the dce equipment is being interfaced to a dte terminal which does not support the scte signal, (e.g., the XRT4500 is now operating in the 2- clock mode), and if the dce/dte interface config- uration settings are such that the txd-to-txc set- up time requirements of the dce scc are being vio- lated, then the user can eliminate this problem by in- voking the clock invert feature of the XRT4500. 1.3.7 the latch mode of operation the latch mode of operation permits the user to latch the state of the mode control input pins (m[2:0]) into the XRT4500 internal circuitry. this feature frees up of the signals, driving the m[2:0] input pins (pins 6, 5, and 4) for other purposes. because of this feature, it is permissible to control the state of the m[2:0] input pins via certain signals within a bi-directional data bus (which is controlled by a microprocessor or microcontroller). the user invokes this feature by driving the latch input pin (pin 44) from low to high. during this low to high transition, the contents of the m[2:0] input pins will be locked (or latched) into internal cir- cuitry within the XRT4500. at this point (as long as the latch input pin remains high) the user's sys- tem can do other things with the signal which are also driving the m[2:0] without affecting the behavior the XRT4500. the user disables the latch feature by driving the latch input pin, from high to low. once the latch input pin is low, then the behavior of the XRT4500 will be dictated by the state of the m[2:0] input pins. 1.3.8 the registered mode of operation the XRT4500 includes a feature which is known as registered mode operation. the user can enable the registered mode by setting the reg input pin high. conversely, the user can disable the regis- tered mode by setting the reg input pin low. if the user enables the registered mode, then the following things will happen. a. the XRT4500 will be configured to sample and latch the contents of the tx5d and tx8d input pins, upon the rising edge of the reg_clk input signal. b. the XRT4500 will be configured to output data (to the scc) via the rx5d and rx8d output pins, up- on the rising edge of the reg_clk signal. this feature is useful in application, which use a scc or a microcontroller (that requires an external clock signal to sample the dsr and the ri (or tm) sig- nals. further, this feature also configures the XRT4500 to sample the state of the dtr and the rl signal upon the rising edge of an external clock signal. if the user invokes this feature, then the relationship between the XRT4500 and the scc/microprocessor is as depicted below in figure 31. f igure 31. a n i llustration of the e ffective i nterface between the XRT4500 and the scc/m icropro - cessor when the r egistered m ode is enabled tx5d rx5d tx8d rx8d reg_clk m m m m c / m m m m p dtr_signal dsr_signal rl_signal ri_signal external clock XRT4500
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 59 a system design similar to that presented below in figure 32, will accomplish the exact same function/re- lationship between another multi-protocol transceiver ic and the scc/microprocessor. 1.3.9 the internal oscillator the XRT4500 includes an internal oscillator that can be used to support dte stand-alone testing/ diagnostics operations. the user can enable the internal oscillator feature (within the XRT4500) by pulling the osc_en input pin (pin 53) low. conversely, the user can disable the internal oscillator feature by pulling the osc_en input pin high. if the user enables this feature, then the XRT4500 will synthesize a clock signal (of frequencies ranging from 32khz to 64khz). further, this clock signal will be out- put via the rx2d and the rx3d output pins. fig- ure 1.20 presents an illustration of the XRT4500 (while interfaced to the dte scc) when the internal oscillator is enabled. f igure 32. a n i llustration of the n ecessary g lue l ogic required to design a feature similar to that offered by the r egistered m ode , when using a different m ulti - protocol s erial n etwork i nterface ic c/p serial network interface device dtr_signal dsr_signal rl_signal ri_signal d-flip-flops clock q q q q clk clk clk clk clock source dte mode
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 60 if the user enables the internal oscillator, within the XRT4500, then the XRT4500 will output between a 32khz and a 64khz clock signal via the rx2d and rx3d signals. when the XRT4500 is interfaced to the dte scc, this translates into the XRT4500 generating the timing signals for txc and the rxc input signals. as a consequence, the dte scc is provided with all of the requisite timing signals that it would normally have, if it were interfaced to a dce terminal. this feature per- mits the user to implement a wide variety of diagnostic programs for dte equipment stand-alone testing. n ote : the internal oscillator feature is only available if the XRT4500 has been configured to operate in the dte mode. 1.3.10 glitch filters occasional extraneous glitches on control/handshake signal inputs such as cts, rts, dtr and dsr can have damaging effects on the integrity of a connection. the XRT4500 is equipped with lowpass filters on the input of each of the receivers for the control and handshake signals. these filters eliminate glitches which are narrower than 10s. the user may disable these filters by setting en_fltr to logic 0. 1.3.11 data inversion similar to txc, there is a provision in the XRT4500 to invert the txd and rxd signals. once the setting the dtinv* input to logic 0 enables an inverter at the output of rx1 and input of tx1. 1.3.12 data interlude similar to txc, there is a provision in the XRT4500 to invert the txd and rxd signals. once the setting the dtinv* input to logic 0 enables an inverter at the out- put of rx1 and input of tx1. 2.0 receiver and transmitter specifications table 3 and table 4, which are for the XRT4500 re- ceiver and transmitter sections respectively, summa- rize the electrical requirements for v.35, v.11, v.10, and rs232 interfaces. these tables provide virtually all of the electrical information necessary to describe these 4 interfaces in a concise form. 3.0 v.10\v.28 output pulse rise and fall time control slew_cntl (pin 47) is an analog output that con- trols transmitter pulse rise and fall time for the v.10 and v.28 modes. connecting a resistor, rslew, hav- ing a value between 0 and 200 k w from this pin to ground controls the rise/fall times for v.10 and the slew rate for v.28 as shown in figure 34 and figure 35 respectively. f igure 33. i llustration of the i nternal o scillators within the XRT4500 scc (l) XRT4500 rx1 rx2 rx3 tx2 tx1 txd scte txc_in rxc_in rxd_in 74 73 txd scte txc rxc rxd osc osc osc osc dte
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 61 4.0 the high-speed rs232 mode f igure 34. v.10 r ise /f all t ime as a f unction of rslew 10k 1 10 100 1 10 3 r (ohms) v.10 rise/fall time (us) 100k 1 meg f igure 35. v.28 s lew r ate o ver 3 v o utput r ange with 3 k w in p arallel with 2500 p f l oad as a f unction of rslew 10k 100k 1 meg 0.01 0.1 1 10 r (ohms) v. 28 sle w ra te (v/ us)
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 62 when e_232h (pin 55) is set to logic 0 in rs232 mode, the transmitters are configured to operate in a special high-speed rs232 mode that can drive loads of 3000 w in parallel with 1000pf at speeds up to 256 khz. 5.0 internal cable terminations XRT4500 has fully integrated receiver and transmitter cable terminations for high speed signals (rxd, txd, rxc, txc, scte). therefore, no external resistors and/or switches are necessary to implement the prop- er line termination. the schematic diagrams given in figures 26 and 27 show the effective receiver and transmitter terminations respectively for each mode of operation. when a specific electrical interface is se- lected by m0, m1 and m2, the termination required for that interface is also automatically chosen. the XRT4500 eliminates double termination problems and makes point to midpoint operation possible in the v.11 mode by providing the option for disabling the in- ternal input termination on high speed receivers. 6.0 operational scenarios visualizing features such as clock/data inversion, echoed clock, and loopbacks, in dte and dce modes makes configuring the XRT4500 a non-trivial task. a series of 48 system level application diagrams located at the end of the data sheet called scenari- os assist users in understanding the benefits of these different features. the internal XRT4500 con- nections required for a particular scenario are made through mux1 and mux2 that are shown on the block diagrams given in figures 2 and 3 respectively. table 8 contains the signal routing information versus control input logic level for mux1 and table 9 con- tains similar information for mux2. 7.0 applications information traditional interfaces either require different transmit- ters and receivers for each electrical standard, or use complicated termination switching methods to change modes of operation. mechanical switching schemes, which are expensive and inconvenient, include relays, and custom cables with the terminations located in the connectors. electrical switching circuits using fets are difficult to implement because the fet must remain off when the signal voltage exceeds the supply voltage and when the interface power is off. the XRT4500 uses innovative, patented circuit de- sign techniques to solve the termination switching problem. it includes internal circuitry that may be con- trolled by software to provide the correct terminations for v.10 (rs423), v.11 (rs422), v.28 (rs232), and v.35 electrical interfaces. the schematic diagrams given in figures 26 and 27 conceptually show the switching options for the high-speed receiver input and transmitter output terminations respectively. ad- ditionally, tables 4 and 5 provide a summary of re- ceiver and transmitter specifications respectively for the different electrical modes of operation. v.10 (rs423) interface figure 28 shows a typical v.10 (rs423) interface. this configuration uses an unbalanced cable to con- nect the transmitter txa output to the receiver rxa input. the b outputs and inputs that are present on the differential transmitters and receivers contained in the XRT4500 are not used. the system ground pro- vides the signal return path. the receiver input resis- tance is 10 k w nominal and no other cable termina- tion is normally used for the v.10 mode. v.11 (rs422) interface figure 29 shows a typical v.11 (rs422) interface. this configuration uses a balanced cable to connect the transmitter txa and txb outputs to the receiver rxa and rxb inputs respectively. the XRT4500 includes provisions for adding a 125 w terminating resistor for the v.11 mode. although this resistor is optional in the v.11 specification, it is necessary to prevent reflections that would corrupt signals on high-speed clock and data lines. the differential receiver input resistance without the optional termination is 20 k w nominal. v.28 (rs232) interface figure 28 shows a typical v.28 (rs232) interface. this configuration uses an unbalanced cable to con- nect the transmitter txa output to the receiver rxa input. the b outputs and inputs that are present on the differential transmitters and receivers contained in the XRT4500 are not used. the system ground pro- vides the signal return path. the receiver b input is internally connected to a 1.4 v reference source to provide a 1.4 v threshold. the receiver input resis- tance is 5 k w nominal and no other cable termination is normally used for the v.28 mode. v.35 interface figure 30 shows a typical v.35 interface. this configu- ration uses a balanced cable to connect the transmit- ter txa and txb outputs to the receiver rxa and rxb inputs respectively. the XRT4500 internal termi- nations meets the following v.35 requirements. the receiver differential input resistance is 100 w 10 w and the shorted-terminal resistance (rxa and rxb connected together) to ground is 150 w 15 w . the transmitter differential output resistance is 100 w 10 w and the shorted-terminal resistance (txa and txb connected together) to ground is 150 w 15 w . the junction of the 3 resistors (cmtx) on the transmit termination is brought out to pins 61 and 66 for tx1
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 63 and tx2 respectively. figure 30 shows how capacitor c having a value of 100 to 1000 pf bypasses this point to ground to reduce common mode noise. this capacitor shorts current caused by differential driver rise and fall time or propagation delay miss-match di- rectly to ground. if it was not present, the flow of this current through the 125 w resistor to ground would cause common mode voltage spikes at the txa and txb outputs. f igure 36. r eceiver t ermination r1 20 s1 rxxa rxxb r3 85 r4 30 r6 125 s3 r2 20 s2 r4 30 r8 10k s4 r10 4k r11 6k r9 4k r12 6k rx t able 6: r eceiver s witches m ode s witches s1 s2 s3 s4 v.35 closed closed open open v.11 terminated open open closed open v.11 unterminated open open open open v.10 open open open open v.28 open open open closed
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 64 f igure 37. t ransmitter t ermination txxa txxb s1 r1 50 r3 125 s2 r2 50 tx t able 7: t ransmitter s witches m ode s witches s1 s2 v.35 closed closed v.11/v.10/v.28 open open f igure 38. t ypical v.10 or v.28 i nterface (r1 = 10 k w in v. 1 0 and 5 k w in v.28) f igure 39. t ypical v.11 i nterface (t ermination r esistor , r1, is o ptional .)
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 65 n ote : all resistors shown above are internal to the XRT4500 f igure 40. t ypical v. 3 5 i nterface 0.1uf t able 8: mux1 c onnection t able s cenario n umber l ogic level a pplied to c ontrol i nput n ame /p in n umber s ignal s ource for o utput n ame /p in n umber dce/ dte 31 ec 34 2ck/ 3ck 50 lp 18 ck inv 54 dt inv 55 en_o sc 53 rx1d 1 tx1b-tx1a 62, 63 rx2d 74 tx2b-tx2a 65, 64 rx3d 73 tr3b-tr3a 71, 70 1 0101111rx1b-rx1a tx1d rx2b-rx2a tx2d tr3b-tr3a x 2 1101111rx1b-rx1a tx1d rx2b-rx2a tx2d x tx3d 3 0100111 tx1d rx1b-rx1a tx2d rx2b-rx2atr3b-tr3a x 4 1100111 tx1d rx1b-rx1a tx2d rx2b-rx2a x tx3d 5 0101011rx1b-rx1a tx1d rx2b-rx2a tx2d (tr3b-tr3a)* x 6 1101011rx1b-rx1a tx1d rx2b-rx2a tx2d x (tx3d)* 7 0100011 tx1d rx1b-rx1a tx2d rx2b-rx2a(tr3b-tr3a)* x 8 1100011 tx1d rx1b-rx1a tx2d rx2b-rx2a x (tx3d)* 9 0111111rx1b-rx1a tx1d rx2b-rx2a x tr3b-tr3a x 10 1111111rx1b-rx1a tx1d tx3d tx2d x tx3d 11 0110111 tx1d rx1b-rx1a tx2d x tr3b-tr3a x 12 1110111 tx1d rx1b-rx1a tx2d tx3d x tx3d 13 0111011rx1b-rx1a tx1d rx2b-rx2a x (tr3b-tr3a)* x 14 1111011rx1b-rx1a tx1d tx3d tx2d x (tx3d)* 15 0110011 tx1d rx1b-rx1a tx2d x (tr3b-tr3a)* x 16 1110011 tx1d rx1b-rx1a tx2d tx3d x (tx3d)* 17 0 1 x 1 1 1 1 rx1b-rx1a tx1d rx2b-rx2a x rx2b-rx2a x 18 1 1 x 1 1 1 1 rx1b-rx1a tx1d tx2d tx2d x x 19 0 1 x 0 1 1 1 tx1d rx1b-rx1a tx2d x tr3b-tr3a x 20 1 1 x 0 1 1 1 tx1d rx1b-rx1a tx2d rx2b-rx2a x x
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 66 n otes : 1. table entries are inputs to mux1. column headings are outputs. 2. signal names ending with a or b are analog inputs or outputs. signal names ending with d are digital 21 0 1 x 1 0 1 1 rx1b-rx1a tx1d rx2b-rx2a x (rx2b-rx2a)* x 22 1 1 x 1 0 1 1 rx1b-rx1a tx1d (tx2d)* tx2d x x 23 0 1 x 0 0 1 1 tx1d rx1b-rx1a tx2d x (rx2b-rx2a)* x 24 1 1 x 0 0 1 1 tx1d note 1 tx2d tx2d x x 25 0001111rx1b-rx1a tx1d rx2b-rx2atr3b-tr3atr3b-tr3a x 26 1001111rx1b-rx1a tx1d rx2b-rx2a tx3d x tx3d 27 0000111 tx1d rx1b-rx1atr3b-tr3arx2b-rx2atr3b-tr3a x 28 1000111 tx1d rx1b-rx1a tx3d rx2b-rx2a x tx3d 29 0001011rx1b-rx1a tx1d rx2b-rx2a(tr3b-tr3a)*(tr3b-tr3a)* x 30 1001011rx1b-rx1a tx1d rx2b-rx2a tx3d x (tx3d)* 31 0000011 tx1d rx1b-rx1a(tr3b-tr3a)*rx2b-rx2a(tr3b-tr3a)* x 32 1000011 tx1d rx1b-rx1a tx3d rx2b-rx2a x (tx3d)* 33 0011111rx1b-rx1a tx1d rx2b-rx2a x tr3b-tr3a x 34 1011111rx1b-rx1a tx1d tx3d tx3d x tx3d 35 0010111 tx1d rx1b-rx1atr3b-tr3a x tr3b-tr3a x 36 1010111 tx1d rx1b-rx1a tx3d tx3d x tx3d 37 0011011rx1b-rx1a tx1d rx2b-rx2a x (tr3b-tr3a)* x 38 1011011rx1b-rx1a tx1d tx3d tx3d x (tx3d)* 39 0010011 tx1d rx1b-rx1a(tr3b-tr3a)* x (tr3b-tr3a)* x 40 1010011 tx1d rx1b-rx1a tx3d tx3d x (tx3d)* 41 0 0 x 1 1 1 1 rx1b-rx1a tx1d rx2b-rx2a x rx2b-rx2a x 42 1 0 x 1 1 1 1 rx1b-rx1a tx1d tx3d tx3d x x 43 0 0 x 0 1 1 1 tx1d rx1b-rx1a rx2b-rx2a x rx2b-rx2a x 44 1 0 x 0 1 1 1 tx1d rx1b-rx1a tx3d tx3d x x 45 0 0 x 1 0 1 1 rx1b-rx1a tx1d rx2b-rx2a x (rx2b-rx2a)* x 46 1 0 x 1 0 1 1 rx1b-rx1a tx1d (tx3d)* tx3d x x 47 0 0 x 0 0 1 1 tx1d rx1b-rx1a rx2b-rx2a x rx2b-rx2a x 48 1 0 x 0 0 1 1 tx1d note 1 tx3d tx3d x x xxxxx0 1 invert invert unchanged unchanged unchanged unchanged 0 1 x 0 x x 0 unchanged unchanged unchanged unchanged 32-64 khz unchanged 0 0 x 0 x x 0 unchanged unchanged 32-64 khz unchanged 32-64 khz unchanged t able 8: mux1 c onnection t able (c ontinued ) s cenario n umber l ogic level a pplied to c ontrol i nput n ame /p in n umber s ignal s ource for o utput n ame /p in n umber dce/ dte 31 ec 34 2ck/ 3ck 50 lp 18 ck inv 54 dt inv 55 en_o sc 53 rx1d 1 tx1b-tx1a 62, 63 rx2d 74 tx2b-tx2a 65, 64 rx3d 73 tr3b-tr3a 71, 70
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 67 inputs or outputs. * indicates signal complement. x is don't care. . n otes : 1. table entries are inputs to mux2. 2. column headings are outputs. 3. signal names ending with a or b are analog inputs or outputs. signal names ending with d are digital inputs or outputs. 4. x = dont care (not used) 5. shaded blocks = normal (no loop-back) operating modes for the XRT4500 the XRT4500 multi protocol serial interface device can be configured to operate in a wide variety of modes or scenarios. this document illustrates some of these scenarios and provides the reader with the following information associated with each of these scenarios. ? which pins (on the dce mode XRT4500 and dte mode XRT4500) are used to propagate vari- ous data or clock signals. ? which signals are to be used when operating the XRT4500 in the differential or single-ended modes. ? how does one configure the dce mode and dte mode XRT4500 to operate in these scenarios. n otes : 1. the line signals are drawn with both a solid line and a dashed line. both lines are used to transmit and receive differential mode signals. however, the solid line identifies the signal that should be used, when operating the transmitter in the sin- gle-ended mode. 2. each scenario includes a table that indicates how to configure the XRT4500 into each of these modes, by specifying the appropriate logic states for ec , 2ck/3ck , lp , ckinv , dtinv , and en_osc . 3. in all, 48 scenarios have been defined for the XRT4500 device. currently, this document only lists a subset of these scenarios. further versions of the XRT4500 data sheet will include this information for all 48 scenarios. t able 9: mux2 c onnection t able (rx4-rx7, tx4-tx7), o utput v ersus i nput s cenario number c ontrol i nput / p in n umber s ignal s ource for o utput n ame /p in n umber dce/ dte lp rx4d tx4b- tx4a rx5d tx5b- tx5a rx67d tr6b-tr6a tr7 31 18 40 10, 11 33 13, 12 32 30, 29 27 a 0 0 tx4d rx4b- rx4a tx5d tr6b- tr6a tx5d x tx76d b01 rx4b- rx4a tx4d rx5b- rx5a tx5d tr6b- tr6a xtx76d c 1 0 tx4d rx4b- rx4a tx76d rx5b- rx5a tr7 rx5b-rx5a x d11 rx4b- rx4a tx4d rx5b- rx5a tx5d tr7 tx76d x
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 68 f igure 41. s cenario a, mux2, (dce/dte = 0, lp = 0) scenario a mux2 (dce/dte = 0, lp = 0) rx8d rx8i 25 23 rx8 filter gnd rx1,2,3 3 rx5b rx5d rx5a 36 33 35 rx5 filter rx67d 32 rx4,5,6,7 rx7 rx6 filter filter 75 en_fltr 8 tx4d 11 tx4a tx4b 10 tx4 15 tx5d 12 tx5a tx5b 13 27 tr7 tx7 tx5 9 vdd tx4,5,6,7,8 29 tr6a tr6b 30 tx6 28 tx76d v.11 (rx1,2,3) termination 80 en_term digital mux 2 glitch filter 48 en_out 17 tx8d 19 tx8o gnd 14 tx4,5,6,7,8 tx8 20 vdd rx4b rx4d rx4a 37 40 38 rx4 filter
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 69 f igure 42. s cenario b, mux2, (dce/dte = 0, lp = 1), l oop b ack n ot enabled rx8d rx8i 25 23 rx8 filter gnd rx1,2,3 3 rx5b rx5d rx5a 36 33 35 rx5 filter rx67d 32 rx4,5,6,7 rx7 rx6 filter filter 75 en_fltr 8 tx4d 11 tx4a tx4b 10 tx4 15 tx5d 12 tx5a tx5b 13 27 tr7 tx7 tx5 9 vdd tx4,5,6,7,8 29 tr6a tr6b 30 tx6 28 tx76d v.11 (rx1,2,3) termination 80 en_term digital mux 2 glitch filter 48 en_out 17 tx8d 19 tx8o gnd 14 tx4,5,6,7,8 tx8 20 vdd rx4b rx4d rx4a 37 40 38 rx4 filter scenario b mux2 (dce/dte = 0, lp = 1) loop back not enabled
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 70 f igure 43. s cenario c, mux2, (dce/dte = 1, lp = 0) scenario c mux2 (dce/dte = 1, lp = 0) rx8d rx8i 25 23 rx8 filter gnd rx1,2,3 3 rx5b rx5d rx5a 36 33 35 rx5 filter rx67d 32 rx4,5,6,7 rx7 rx6 filter filter 75 en_fltr 8 tx4d 11 tx4a tx4b 10 tx4 15 tx5d 12 tx5a tx5b 13 27 tr7 tx7 tx5 9 vdd tx4,5,6,7,8 29 tr6a tr6b 30 tx6 28 tx76d v.11 (rx1,2,3) termination 80 en_term digital mux 2 glitch filter 48 en_out 17 tx8d 19 tx8o gnd 14 tx4,5,6,7,8 tx8 20 vdd rx4b rx4d rx4a 37 40 38 rx4 filter
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 71 f igure 44. s cenario d, mux2, (dce/dte = 1, lp = 1), l oop b ack n ot enabled scenario d mux 2 (dce/dte = 1, lp = 1) loop back not enabled rx8d rx8i 25 23 rx8 filter gnd rx1,2,3 3 rx5b rx5d rx5a 36 33 35 rx5 filter rx67d 32 rx4,5,6,7 rx7 rx6 filter filter 75 en_fltr 8 tx4d 11 tx4a tx4b 10 tx4 15 tx5d 12 tx5a tx5b 13 27 tr7 tx7 tx5 9 vdd tx4,5,6,7,8 29 tr6a tr6b 30 tx6 28 tx76d v.11 (rx1,2,3) termination 80 en_term digital mux 2 glitch filter 48 en_out 17 tx8d 19 tx8o gnd 14 tx4,5,6,7,8 tx8 20 vdd rx4b rx4d rx4a 37 40 38 rx4 filter
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 72 f igure 45. s erial i nterface s ignals and c onnector p in -o ut serial interface signals and connector pin-out XRT4500 standard rs-232 eia-574 rs-530 rs-449 v.35 x.21 XRT4500 XRT4500 related standards v.24 tia-574 rs422, rs423 rs422, rs423 v.10, v.11, v.28 v.11, x.26 connector db-25 db-9 db-25 db-37 34-pin 15-pin dte dce signal name abrev. source pin #, circuit pin # pin #, circuit pin #, circuit pin, ccitt# pin #, circuit pin #, circuit pin #, circuit shield --- 1, --- 1, --- 1, --- a, --- 1, --- --, --- --, --- transmitted data txd dte 2, ba 3 2, ba (a) 14, ba (b) 4, sd (a) 22, sd (b) p, 103 s, 103 2, circuit t (a) 9, circuit t (b) 63, tx1a 62, tx1b 78, rx1a 79, rx1b received data rxd dce 3, bb 2 3, bb (a) 16, bb (b) 6, rd (a) 24, rd (b) r, 104 t, 104 4, circuit r (a) 11, circuit r (b) 78, rx1a 79, rx1b 63, tx1a 62, tx1b request to send (control for x.21) rts dte 4, ca 7 4, ca (a) 19, ca (b) 7, rs (a) 25, rs (b) c, 105 3, circuit c (a) 10, circuit c (b) 11, tx4a 10, tx4b 37, rx4a 38, rx4b clear to send (indication for x.21) cts dce 5, cb 8 5, cb (a) 13, cb (b) 9, cs (a) 27, cs (b) d, 106 5, circuit i (a) 12, circuit i (b) 37, rx4a 38, rx4b 11, tx4a 10, tx4b dce ready dsr dce 6, cc 6 6, cc (a) 22, cc (b) 11, dm (a) 29, dm (b) e, 107 36, rx5a 35, rx5b 12, tx5a 13, tx5b dte ready dtr dte 20, cd 4 20, cd (a) 23, cd (b) 12, tr (a) 30, tr (b) h, 108 * 12, tx5a 13, tx5b 36, rx5a 35, rx5b signal ground *** --- 7, ab 5 7, ab 19, sg b, 102 8, circuit g 3, 14, 59, 72 3, 14, 59, 72 received line signal detector dcd dce 8, cf 1 8, cf (a) 10, cf (b) 13, rr (a) 31, rr (b) f, 109 29, tr6a 30, tr6b 29, tr6a 30, tr6b transmitter signal element timing txc dce 15, db 15, db (a) 12, db (b) 5, st (a) 23, st (b) y, 114 aa, 114 7, circuit b (a) ** 14, circuit b (b) ** 70, tr3a 71, tr3b 70, tr3a 71, tr3b received signal element timing rxc dce 17, dd 17, dd (a) 9, dd (b) 8, rt (a) 26, rt (b) v, 115 x, 115 6, circuit s (a) 13, circuit s (b) 77, rx2a 76, rx2b 64, tx2a 65, tx2b local loop-back ll dte 18, ll 18, ll 10, ll l, 141 * 27, tr7 27, tr7 remote loop-back rl dte 21, rl 21, rl 14, rl n, 140 * 19, tx8o 25, rx8i ring indicator ci dce 22, ce 9 --, ---- --, --- j , 125 * --, --- transmit signal element timing scte dte 24, da 24, da (a) 11, da (b) 17, tt (a) 35, tt (b) u, 113 * w, 113 * 7, circuit x (a) ** 14, circuit x (b) ** 64, tx2a 65, tx2b 77, rx2a 76, rx2b test mode tm dce 25, tm 25, tm 18, tm nn, 142 * 25, rx8i 19, tx8o load resistance rl=100 w rl=120 w rl=100 w rl=120 w signal amplitude 5 to 15 v 0.55 vpp speed per standard 20 to 150kbps rs422: 10mbp rs423: 100kbps std: 48kpbs max: 10mbps v.11: 10mbps XRT4500 speed 256 kbps v.10: 120 kbps v.11: 20 mbps mode selection * optional signal ** only one of the two x.21 signals (circuit b or x) can be implemented and be active at one time *** connect the signal ground to the pcb ground plane of the XRT4500. (pins 3, 14, 59 and 72 are the analog grounds for the receivers and transmitters on the XRT4500)
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 73 f igure 46. s erial i nterface c onnector d rawings 30 25 20 37 33 19 15 10 5 1 nn l r v z dd jj f b mm ll bb d j n t x ff k p u y cc hh a e kk ee c h m s w aa 13 7 1 25 20 14 1 8 15 9 serial interface connector drawings x.21 connector (iso 4903) dte connector - db-15 pin male dce connector - db-15 pin female rs-449 connector (iso 4902) dte connector face - db-37 pin male dce connector face - db-37 pin female v.35/iso 2593 connector dte connector face - 34 pin male dce connector face - 34 pin female rs-232 & eia-530- connector (iso 2110) dte connector - db-25 pin male dce connector - db-25 pin female f igure 46 a f igure 46 b f igure 46 d f igure 46 c
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 74 f igure 47. eia-530 c onnection d iagram for XRT4500 eia-530 connection diagram for XRT4500 rx1b rx1a tr3a tx1a tx1b rx4a tx2a tx4a tr7 tx5a rx4b rx5a tr6a rx8i tx2b tx5b tr6b rx5b rx2b rx2a tr3b tx8o tx4b 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 ll a txd b txd a txc a rxd a rxd b rts a rxc a cts a dsr a rts b dtr a dcd a dsr b dcd b dtr b txc b cts b rl a rxc b scte b scte a ri 3, 14, 59, 77 XRT4500 62 63 70 78 79 11 77 37 27 36 10 12 29 19 76 35 30 13 65 64 71 25 38 tx1b tx1a tr3a rx1a rx1b tx4a rx2a rx4a tr7 rx5a tx4b tx5a tr6a tx8o rx2b rx5b tr6b tx5b tx2b tx2a tr3b rx8i rx4b 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 scte b txd a txd b scte a rxd b rxd a rxc b rxc a txc b txc a cts b cts a dsr b dsr a dcd b dcd a ri rts a rts b dtr b dtr a ll a rl a 79 78 70 63 62 37 64 11 27 12 38 36 29 25 65 13 30 35 76 77 71 19 10 3, 14, 59, 77 XRT4500 db25 dce mode p8 db25 dte mode p4 dte mode dce mode shield shield
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 75 f igure 48. rs-232 c onnection d iagram for XRT4500 rs-232 connection diagram for XRT4500 rx1a tr3a tx1a rx4a tx2a tx4a tr7 tx5a rx5a tr6a rx8i tx8o 25 21 8 20 7 6 18 5 17 4 3 15 2 1 ll a txd a txc a rxd a rts a rxc a cts a dsr a dtr a dcd a dsr b rl a ri 3, 14, 59, 77 XRT4500 63 70 78 11 77 37 27 36 12 29 19 64 25 tx1a tr3a rx1a tx4a rx2a rx4a tr7 rx5a tx5a tr6a tx8o tx2a rx8i 25 24 21 8 20 7 6 18 5 17 4 3 15 2 1 scte b txd a scte a rxd a rxc a txc a cts a dsr a dcd a ri rts a dtr a ll a rl a 78 70 63 37 64 11 27 12 36 29 25 19 3, 14, 59, 77 XRT4500 p4 dte mode db25 dce mode p8 db25 dce mode dte mode shield shield
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 76 s cenarios 1 & 2 n ormal : 3- clock dce/dte i nterface o peration i nput p in s ettings n ote : 1. when m0=1, m2=1, m2=0 the XRT4500 is in the 1 clock (x.21) mode and the 2ck/3ck input pin is ignored. 2. (see table 8. mux connection table) dte (#1) dce (#2) p in # n ame s tate d escription p in # n ame s tate d escription 31 dce/dte 0 dte 31 dce/dte 1dce 34 ec 1 no echo 34 ec 1 no echo 50 2ck/3ck 0 3 clock 50 2ck/3ck 03 clock 18 lp 1 no loopback 18 lp 1 no loopback 54 ckinv 1no invert 54ckinv 1no invert 55 dtinv 1 no invert 55 dtinv 1no invert 53 oscen 1 no internal osc 53 oscen 1 no internal osc hdlc (r) hdlc (l) XRT4500 XRT4500 rx1 tx1 rx2 tx2 rx3 tx3 rx2 tx2 rx1 tx1 txd scte txc rxc rxd txd scte txc rxc rxd 60 67 73 74 1 78 79 77 76 70 71 64 65 63 62 1 74 68 67 60 63 62 64 65 70 71 77 76 78 79 txd scte txc rxc rxd dte (#1) dce (#2)
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 77 s cenario 3 &2 dte l oop -b ack m ode i nput p in s ettings n ote : when m0=1, m2=1, m2=0 the XRT4500 is in the 1 clock (x.21) mode and the 2ck/3ck input pin is ignored. dte (#3) dce (#2) p in # n ame s tate d escription p in # n ame s tate d escription 31 dce/dte 0 dte 31 dce/dte 1 dce 34 ec 1 no echo 34 ec 1 no echo 50 2ck/3ck 0 3 clock 50 2ck/3ck 03 clock 18 lp 0 loopback 18 lp 1 no loopback 54 ckinv 1 no invert 54 ckinv 1no invert 55 dtinv 1 no invert 55 dtinv 1no invert 53 oscen 1 no internal osc 53 oscen 1 no internal osc hdlc (r) hdlc (l) XRT4500 XRT4500 rx1 tx1 rx2 tx2 rx3 tx3 rx2 tx2 rx1 tx1 txd scte txc rxc rxd txd scte txc rxc rxd 60 67 73 74 1 78 79 77 76 70 71 64 65 63 62 1 74 68 67 60 63 62 64 65 70 71 77 76 78 79 txd scte txc rxc rxd dte (#3) dce (#2) mux 1
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 78 s cenario 4 c omments : dce l oop -b ack m ode i nput p in s ettings n ote : when m0=1, m2=1, m2=0 the XRT4500 is in the 1 clock (x.21) mode and the 2ck/3ck input pin is ignored. dte (#1) dce (#4) p in # n ame s tate d escription p in # n ame s tate d escription 31 dce/dte 0 dte 31 dce/dte 1 dce 34 ec 1 no echo 34 ec 1 no echo 50 2ck/3ck 0 3 clock 50 2ck/3ck 03 clock 18 lp 1 no loopback 18 lp 0 loopback 54 ckinv 1 no invert 54 ckinv 1no invert 55 dtinv 1 no invert 55 dtinv 1no invert 53 oscen 1 no internal osc 53 oscen 1 no internal osc hdlc (r) hdlc (l) XRT4500 XRT4500 rx1 tx1 rx2 tx2 rx3 tx3 rx2 tx2 rx1 tx1 txd scte txc rxc rxd txd scte txc rxc rxd 60 67 73 74 1 78 79 72 76 70 71 64 65 63 62 1 74 68 67 60 63 62 64 65 70 71 77 76 78 79 txd scte txc rxc rxd dce (#4) dte (#1) mux 1
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 79 s cenario 5 & 2 c omments : txc c lock i nversion in dte m ode i nput p in s ettings n ote : when m0=1, m2=1, m2=0 the XRT4500 is in the 1 clock (x.21) mode and the 2ck/3ck input pin is ignored. dte (#5) dce (#2) p in # n ame s tate d escription p in # n ame s tate d escription 31 dce/dte 0 dte 31 dce/dte 1 dce 34 ec 1 no echo 34 ec 1 no echo 50 2ck/3ck 0 3 clock 50 2ck/3ck 03 clock 18 lp 1 no loopback 18 lp 1 no loopback 54 ckinv 0invert 54ckinv 1no invert 55 dtinv 1 no invert 55 dtinv 1no invert 53 oscen 1 no internal osc 53 oscen 1 no internal osc hdlc (r) hdlc (l) XRT4500 XRT4500 rx1 tx1 rx2 tx2 rx3 tx3 rx2 tx2 rx1 tx1 txd scte txc rxc rxd txd scte txc rxc rxd 60 67 73 74 1 78 79 72 76 70 71 64 65 63 62 1 74 68 67 60 63 62 64 65 70 71 77 76 78 79 txd scte txc rxc rxd dce (#2) dte (#5)
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 80 s cenario 6 c omments : txc c lock i nversion in dce m ode i nput p in s ettings n ote : when m0=1, m2=1, m2=0 the XRT4500 is in the 1 clock (x.21) mode and the 2ck/3ck input pin is ignored. dte (#1) dce (#6) p in # n ame s tate d escription p in # n ame s tate d escription 31 dce/dte 0 dte 31 dce/dte 1 dce 34 ec 1 no echo 34 ec 1 no echo 50 2ck/3ck 0 3 clock 50 2ck/3ck 03 clock 18 lp 1 no loopback 18 lp 1 no loopback 54 ckinv 1 no invert 54 ckinv 0invert 55 dtinv 1 no invert 55 dtinv 1no invert 53 oscen 1 no internal osc 53 oscen 1 no internal osc dte (#1) hdlc (l) XRT4500 XRT4500 rx1 tx1 rx2 tx2 rx3 tx3 rx2 tx2 rx1 tx1 txd scte txc rxc rxd txd scte txc rxc rxd 60 67 73 74 1 78 79 72 76 70 71 64 65 63 62 1 74 68 67 60 63 62 64 65 70 71 77 76 78 79 txd scte txc rxc rxd dce (#6) hdlc (r)
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 81 s cenario 7 & 2 i nput p in s ettings n ote : when m0=1, m2=1, m2=0 the XRT4500 is in the 1 clock (x.21) mode and the 2ck/3ck input pin is ignored. dte (#7) dce (#2) p in # n ame s tate d escription p in # n ame s tate d escription 31 dce/dte 0 dte 31 dce/dte 1 dce 34 ec 1 no echo 34 ec 1 no echo 50 2ck/3ck 0 3 clock 50 2ck/3ck 03 clock 18 lp 0 loopback 18 lp 1 no loopback 54 ckinv 0invert 54ckinv 1no invert 55 dtinv 1 no invert 55 dtinv 1no invert 53 oscen 1 no internal osc 53 oscen 1 no internal osc hdlc (r) hdlc (l) XRT4500 XRT4500 rx1 tx1 rx2 tx2 rx3 tx3 rx2 tx2 rx1 tx1 txd scte txc rxc rxd txd scte txc rxc rxd 60 67 73 74 1 78 79 72 76 70 71 64 65 63 62 1 74 68 67 60 63 62 64 65 70 71 77 76 78 79 txd scte txc rxc rxd dce (#2) dte (#7) mux 1
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 82 s cenario 8 i nput p in s ettings n ote : when m0=1, m2=1, m2=0 the XRT4500 is in the 1 clock (x.21) mode and the 2ck/3ck input pin is ignored. dte (#1) dce (#8) p in # n ame s tate d escription p in # n ame s tate d escription 31 dce/dte 0 dte 31 dce/dte 1 dce 34 ec 1 no echo 34 ec 1 no echo 50 2ck/3ck 0 3 clock 50 2ck/3ck 03 clock 18 lp 1 no loopback 18 lp 0 loopback 54 ckinv 1 no invert 54 ckinv 0invert 55 dtinv 1 no invert 55 dtinv 1no invert 53 oscen 1 no internal osc 53 oscen 1 no internal osc hdlc (r) hdlc (l) XRT4500 XRT4500 rx1 tx1 rx2 tx2 rx3 tx3 rx2 tx2 rx1 tx1 txd scte txc rxc rxd txd scte txc rxc rxd 60 76 73 74 1 78 79 72 76 70 71 64 65 63 62 1 74 68 67 60 63 62 64 65 70 71 77 76 78 79 txd scte txc rxc rxd dce (#8) dce (#1) mux 1
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 83 s cenario 9 & 10 c omments : 2 c lock m ode o peration w ithin the dce m ode . t his feature is u seful f or a pplications t hat i nterface to a d evice w hich d oes n ot s upply scte c lock s ignal i nput p in s ettings n ote : when m0=1, m2=1, m2=0 the XRT4500 is in the 1 clock (x.21) mode and the 2ck/3ck input pin is ignored. dte (#9) dce (#10) p in # n ame s tate d escription p in # n ame s tate d escription 31 dce/dte 0 dte 31 dce/dte 1 dce 34 ec 1 no echo 34 ec 1 no echo 50 2ck/3ck x dont care 50 2ck/3ck 12 clock 18 lp 1 no loopback 18 lp 1 no loopback 54 ckinv 1 no invert 54 ckinv 1no invert 55 dtinv 1 no invert 55 dtinv 1no invert 53 oscen 1 no internal osc 53 oscen 1 no internal osc dce (#10) hdlc (l) XRT4500 XRT4500 rx1 tx1 rx2 tx2 rx3 tx3 rx2 tx2 rx1 tx1 txd scte txc rxc rxd txd scte txc rxc rxd 60 67 73 74 1 78 79 72 76 70 71 64 65 63 62 1 74 68 67 60 63 62 64 65 70 71 77 76 78 79 txd txc rxc rxd hdlc (r) dte (#9)
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 84 s cenario 12 i nput p in s ettings n ote : when m0=1, m2=1, m2=0 the XRT4500 is in the 1 clock (x.21) mode and the 2ck/3ck input pin is ignored. dte (#9) dce (#12) p in # n ame s tate d escription p in # n ame s tate d escription 31 dce/dte 0 dte 31 dce/dte 1 dce 34 ec 1 no echo 34 ec 1 no echo 50 2ck/3ck 0 3 clock 50 2ck/3ck 12 clock 18 lp 1 no loopback 18 lp 0 loopback 54 ckinv 1 no invert 54 ckinv 1no invert 55 dtinv 1 no invert 55 dtinv 1no invert 53 oscen 1 no internal osc 53 oscen 1 no internal osc hdlc (r) hdlc (l) XRT4500 XRT4500 rx1 tx1 rx2 tx2 rx3 tx3 rx2 tx2 rx1 tx1 txd scte txc rxc rxd txd scte txc rxc rxd 60 67 73 74 1 78 79 72 76 70 71 64 65 63 62 1 75 68 67 60 63 62 64 65 70 71 77 76 78 79 txd txc rxc rxd dce (#12) dte ( #9 ) mux 1
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 85 s cenario 13 & 10 i nput p in s ettings n ote : when m0=1, m2=1, m2=0 the XRT4500 is in the 1 clock (x.21) mode and the 2ck/3ck input pin is ignored. dte (#13) dce (#10) p in # n ame s tate d escription p in # n ame s tate d escription 31 dce/dte 0 dte 31 dce/dte 1 dce 34 ec 1 no echo 34 ec 1 no echo 50 2ck/3ck 1 2 clock 50 2ck/3ck 12 clock 18 lp 1 no loopback 18 lp 1 no loopback 54 ckinv 0invert 54ckinv 1no invert 55 dtinv 1 no invert 55 dtinv 1no invert 53 oscen 1 no internal osc 53 oscen 1 no internal osc hdlc (r) hdlc (l) XRT4500 XRT4500 rx1 tx1 rx2 tx2 rx3 tx3 rx2 tx2 rx1 tx1 txd scte txc rxc rxd txd scte txc rxc rxd 60 67 73 74 1 78 79 72 76 70 71 64 65 63 62 1 74 68 67 60 63 62 64 65 70 71 77 76 78 79 txd txc rxc rxd dte (#13) dce (#10)
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 86 s cenario 14 c omments : txc c lock i nversion and 2 c lock m ode o peration w ithin t he dce m ode . t his s cenario c an be u sed to r esolve the 2 c lock p ropagation d elay t iming v iolation i ssue . i nput p in s ettings n ote : when m0=1, m2=1, m2=0 the XRT4500 is in the 1 clock (x.21) mode and the 2ck/3ck input pin is ignored. dte dce p in # n ame s tate d escription p in # n ame s tate d escription 31 dce/dte 0 dte 31 dce/dte 1 dce 34 ec 1 no echo 34 ec 1 no echo 50 2ck/3ck 1 2 clock 50 2ck/3ck 12 clock 18 lp 1 no loopback 18 lp 1 no loopback 54 ckinv 1 no invert 54 ckinv 0invert 55 dtinv 1 no invert 55 dtinv 1no invert 53 oscen 1 no internal osc 53 oscen 1 no internal osc hdlc (r) hdlc (l) XRT4500 XRT4500 rx1 tx1 rx2 tx2 rx3 tx3 rx2 tx2 rx1 tx1 txd scte txc rxc rxd txd scte txc rxc rxd 60 67 73 74 1 78 79 72 76 70 71 64 65 63 62 1 74 68 67 60 63 62 64 65 70 71 77 76 78 79 txd txc rxc rxd dte (#13) dce (#14)
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 87 s cenario 16 i nput p in s ettings n ote : when m0=1, m2=1, m2=0 the XRT4500 is in the 1 clock (x.21) mode and the 2ck/3ck input pin is ignored. dte (#9) dce (#16) p in # n ame s tate d escription p in # n ame s tate d escription 31 dce/dte 0 dte 31 dce/dte 1 dce 34 ec 1 no echo 34 ec 1 no echo 50 2ck/3ck 1 2 clock 50 2ck/3ck 12 clock 18 lp 1 no loopback 18 lp 0 loopback 54 ckinv 1 no invert 54 ckinv 0invert 55 dtinv 1 no invert 55 dtinv 1no invert 53 oscen 1 no internal osc 53 oscen 1 no internal osc hdlc (r) hdlc (l) XRT4500 XRT4500 rx1 tx1 rx2 tx2 rx3 tx3 rx2 tx2 rx1 tx1 txd scte txc rxc rxd txd scte txc rxc rxd 60 67 73 74 1 78 79 72 76 70 71 64 65 63 62 1 74 68 67 60 63 62 64 65 70 71 77 76 78 79 txd txc rxc rxd dte (#9) dce (#16) mux 1
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 88 s cenario 17 & 18 c omments : x:21 m ode o peration i nput p in s ettings (1 clock mode ) n ote : when m0=1, m2=1, m2=0 the XRT4500 is in the 1 clock (x.21) mode and the 2ck/3ck input pin is ignored. dte (#17) dce (#18) p in # n ame s tate d escription p in # n ame s tate d escription 31 dce/dte 0 dte 31 dce/dte 1 dce 34 ec 1 no echo 34 ec 1 no echo 50 2ck/3ck x dont care 50 2ck/3ck xdont care 18 lp 1 no loopback 18 lp 1 no loopback 54 ckinv 1 no invert 54 ckinv 1no invert 55 dtinv 1 no invert 55 dtinv 1no invert 53 oscen 1 no internal osc 53 oscen 1 no internal osc hdlc (r) hdlc (l) XRT4500 XRT4500 rx1 tx1 rx2 tx2 rx3 tx3 rx2 tx2 rx1 tx1 txd scte txc rxc rxd txd scte txc rxc rxd 60 67 73 74 1 78 79 72 76 70 71 64 65 64 62 1 74 68 67 60 63 62 64 65 70 71 77 76 78 79 txd rxc rxd dte (#17) dce (#18)
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 89 s cenario 20 i nput p in s ettings (1 clock mode ) n ote : when m0=1, m2=1, m2=0 the XRT4500 is in the 1 clock (x.21) mode and the 2ck/3ck input pin is ignored. dte (#17) dce (#20) p in # n ame s tate d escription p in # n ame s tate d escription 31 dce/dte 0 dte 31 dce/dte 1 dce 34 ec 1 no echo 34 ec 1 no echo 50 2ck/3ck x dont care 50 2ck/3ck xdont care 18 lp 1 no loopback 18 lp 0 loopback 54 ckinv 1 no invert 54 ckinv 1no invert 55 dtinv 1 no invert 55 dtinv 1no invert 53 oscen 1 no internal osc 53 oscen 1 no internal osc hdlc (r) hdlc (l) XRT4500 XRT4500 rx1 tx1 rx2 tx2 rx3 tx3 rx2 tx2 rx1 tx1 txd scte txc rxc rxd txd scte txc rxc rxd 60 67 73 74 1 78 79 72 76 70 71 64 65 63 62 1 74 68 67 60 63 62 64 65 70 71 77 76 78 79 txd rxc rxd dte (#17) dce (#20) mux 1
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 90 s cenario 21 i nput p in s ettings (1 clock mode ) n ote : when m0=1, m2=1, m2=0 the XRT4500 is in the 1 clock (x.21) mode and the 2ck/3ck input pin is ignored. dte (#21) dce (#18) p in # n ame s tate d escription p in # n ame s tate d escription 31 dce/dte 0 dte 31 dce/dte 1 dce 34 ec 1 no echo 34 ec 1 no echo 50 2ck/3ck x dont care 50 2ck/3ck xdont care 18 lp 1 no loopback 18 lp 1 no loopback 54 ckinv 0invert 54ckinv 1no invert 55 dtinv 1 no invert 55 dtinv 1no invert 53 oscen 1 no internal osc 53 oscen 1 no internal osc hdlc (r) hdlc (l) XRT4500 XRT4500 tx1 rx2 tx2 rx3 tx3 rx2 tx2 rx1 tx1 txd scte txc rxc rxd txd scte txc rxc rxd 60 67 73 74 1 78 79 72 76 70 71 64 65 63 62 1 74 68 67 60 63 62 64 65 70 61 77 76 78 79 txd rxc rxd dte (#21) dce (#18) rx1
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 91 s cenario 22 i nput p in s ettings (1 clock mode ) n ote : when m0=1, m2=1, m2=0 the XRT4500 is in the 1 clock (x.21) mode and the 2ck/3ck input pin is ignored. dte (#17) dce (#22) p in # n ame s tate d escription p in # n ame s tate d escription 31 dce/dte 0 dte 31 dce/dte 1 dce 34 ec 1 no echo 34 ec 1 no echo 50 2ck/3ck x dont care 50 2ck/3ck xdont care 18 lp 1 no loopback 18 lp 1 no loopback 54 ckinv 1 no invert 54 ckinv 0invert 55 dtinv 1 no invert 55 dtinv 1no invert 53 oscen 1 no internal osc 53 oscen 1 no internal osc hdlc (r) hdlc (l) XRT4500 XRT4500 rx1 tx1 rx2 tx2 rx3 tx3 rx2 tx2 rx1 tx1 txd scte txc rxc rxd txd scte txc rxc rxd 60 67 73 74 1 78 79 72 76 70 71 64 65 63 62 1 74 68 67 60 63 62 64 65 70 71 77 76 78 79 txd rxc rxd dte (#17) dce (#22)
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 92 s cenario 23 i nput p in s ettings (1 clock mode ) n ote : when m0=1, m2=1, m2=0 the XRT4500 is in the 1 clock (x.21) mode and the 2ck/3ck input pin is ignored. dte (#23) dce (#18) p in # n ame s tate d escription p in # n ame s tate d escription 31 dce/dte 0 dte 31 dce/dte 1 dce 34 ec 1 no echo 34 ec 1 no echo 50 2ck/3ck x dont care 50 2ck/3ck xdont care 18 lp 0 loopback 18 lp 1 no loopback 54 ckinv 0invert 54ckinv 1no invert 55 dtinv 1 no invert 55 dtinv 1no invert 53 oscen 1 no internal osc 53 oscen 1 no internal osc hdlc (r) hdlc (l) XRT4500 XRT4500 rx1 tx1 rx2 tx2 tx3 rx2 tx2 rx1 tx1 txd scte txc rxc rxd txd scte txc rxc rxd 60 67 73 74 1 78 79 72 76 70 71 64 65 63 62 1 74 68 67 60 63 62 64 65 70 61 77 76 78 79 txd rxc rxd dte #23) dce (#18) mux 1 rx3
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 93 s cenario 48 i nput p in s ettings (1 clock mode ) n ote : when m0=1, m2=1, m2=0 the XRT4500 is in the 1 clock (x.21) mode and the 2ck/3ck input pin is ignored. dte (#17) dce (#48) p in # n ame s tate d escription p in # n ame s tate d escription 31 dce/dte 0 dte 31 dce/dte 1 dce 34 ec 1 no echo 34 ec 0echo mode 50 2ck/3ck x dont care 50 2ck/3ck xdont care 18 lp 1 no loopback 18 lp 0 loopback 54 ckinv 1 no invert 54 ckinv 0invert 55 dtinv 1 no invert 55 dtinv 1no invert 53 oscen 1 no internal osc 53 oscen 1 no internal osc hdlc (r) hdlc (l) XRT4500 XRT4500 rx1 tx1 rx2 tx2 rx3 tx3 rx2 tx2 rx1 tx1 txd scte txc rxc rxd txd scte txc rxc rxd 60 67 73 74 1 78 79 72 76 70 71 64 65 63 62 1 74 68 67 60 63 62 64 65 70 61 77 76 78 79 txd rxc rxd dte (#17) dce #48) clk q d
XRT4500 ? ? ? ? multiprotocol serial network interface ic rev. 1.0.7 94 external components used by the XRT4500 function description notes v ss by-pass capacitor 25-47 m f, 12v, smt tantalum -6v switching regulator filter. low esr. (0.20 w max at 100khz) sprague type spr595d476x9025r2t-x schottky diode 1n5819 40v, 1a. must be schottky type inductor 47 or 68 m h smt inductor jw miller pm105-470k or pm105- 680k. coilcraft d03316p-473 current sense resistor 0.5 w , 0.5w, 5% charge pump capacitor 2.2 m f, 25v, smt tantalum +12v charge pump v pp by-pass capacitor 10 m f, 25v, smt tantalum +12v charge pump v dd by-pass capacitor 22 m f, 16v, electrolytic +5v decoupling. (in addition to various 0.1 m f, 50v capacitors) general by-pass capacitors 0.1 m f, 50v panasonic x7r dielectric, 1206 size. digikey pcc104bct-nd
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 95 note: the control dimension is the millimeter column inches millimeters symbol min max min max a 0.055 0.063 1.40 1.60 a 1 0.002 0.006 0.05 0.15 a 2 0.053 0.057 1.35 1.45 b 0.009 0.015 0.22 0.38 c 0.004 0.008 0.09 0.20 d 0.622 0.638 15.80 16.20 d 1 0.547 0.555 13.90 14.10 e 0.0256 bsc 0.65 bsc l 0.018 0.030 0.45 0.75 a 0 7 0 7 60 41 40 21 1 2 0 61 80 d d1 d d1 b e a2 a a1 a seating plane l c 80 lead thin quad flat pack (14 x 14 x 1.4 mm tqfp) rev. 3.00
? ? ? ? XRT4500 multiprotocol serial network interface ic rev. 1.0.7 96 notice exar corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no represen- tation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration purposes and may vary depending upon a users specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support sys- tem or to significantly affect its safety or effectiveness. products are not authorized for use in such applica- tions unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corpo- ration is adequately protected under the circumstances. copyright 2002 exar corporation datasheet september 2002. reproduction, in part or whole, without the prior written consent of exar corporation is prohibited. revisions rev. 1.0.3 -- updated electrical characteristics, made minor text edits. rev. 1.0.4 -- corrected page formatting problems. rev. 1.0.5 -- corrected table anchor format problem page 46 (caused text to hide), replaced tr3 with tr6 page 41. rev. 1.0.6 -- figure 2: supply current vs. temp, edited idd values. rev. 1.0.7 -- table 1, receiver specs v.35-- min signal level = 250mv, max signal peak = 10v, dc rin = 175 w . table 6, switch s4 v.28 changed from open to closed.

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